SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 118

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
9.1
HOST
CONNECTOR
1
2-9
10
11
12
13
14
15
16
17
(1) = Compatible Mode
(3) = High Speed Mode
Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers,
DATA PORT
ADDRESS OFFSET = 00H
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the
internal data bus. The contents of this register are buffered (non inverting) and output onto the PD0
- PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and
output to the host CPU.
STATUS PORT
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register
are latched for the duration of a read cycle. The bits of the Status Port are defined as follows:
Bit 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus.
A logic O means that no time out error has occurred; a logic 1 means that a time out error has been
detected. This bit is cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode
Register 2, 0xF1 in Logical Device 3 Configuration Registers) is ‘0’, writing a one to this bit clears the
TMOUT status bit. Writing a zero to this bit has no effect. If the TIMEOUT_SELECT bit (bit 4 of the
IBM XT/AT Compatible, Bi-Directional and EPP Modes
PIN NUMBER
83
68-75
80
79
78
77
82
81
66
67
refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14 , July
14, 1993. This document is available from Microsoft.
Table 9.1 Parallel Port Connector
STANDARD
nSTROBE
PD<0:7>
nACK
BUSY
PE
SLCT
nALF
nERROR
nINIT
nSLCTIN
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
102
EPP
nWrite
PData<0:7>
Intr
nWait
(User Defined)
(User Defined)
nDatastb
(User Defined)
nRESET
nAddrstrb
ECP
nStrobe
PData<0:7>
nAck
Busy, PeriphAck(3)
PError,
nAckReverse (3)
Select
nAutoFd,
HostAck(3)
nFault (1)
nPeriphRequest (3)
nInit(1)
nReverseRqst(3)
nSelectIn(1,3)
SMSC SCH311X
Datasheet