SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 171

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
15.2
15.3
15.4
If the corresponding bit in both in a PME Wake Status register and the PME Wake Enable Register
are set then the PME Pin Status Register bit is set. If both corresponding PME Pin Status and the PME
Pin Enable Register bit are set then the IO_PME pinIO_PME pin will asserted.
For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is
controlled by the polarity bit of the GPIO control register. For non-inverted polarity (default) the status
bit is set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low
and a low-to-high edge will set the corresponding PME status bits. Status bits are cleared on a write
of '1'.
The PME Wake registers also include status and enable bits for the HW Monitor Block.
See
the keyboard and mouse signals to generate a PME.
There is a bit in the PME Status Register 3 to show the status of the internal “group” SMI signal in the
PME logic (if bit 5 of the SMI_EN2 register is set). This bit, DEVINT_STS, is at bit 3 of the PME_STS3
register. When this bit is clear, the group SMI output is inactive. When bit is set, the group SMI output
is active.The corresponding Wake-up enable bit is DEVINT_EN, is at bit 3 of the PME_EN3 register.
Bit 5 of the SMI_EN2 register must also be set. This bit is cleared on a write of '1'.
The GP42/nIO_PME pin, when selected for the nIO_PME function, can be programmed to be active
high or active low via the polarity bit in the
programmed to be open-drain or push-pull via bit 7 of the
defaults to active low, open-drain output; however the GP42/nIO_PME pin defaults to the GP42
function.
In the SCH311X the nIO_PME pin can be programmed to be an open drain, active low, driver. The
SCH311X nIO_PME pin are fully isolated from other external devices that might pull the signal low;
i.e., the nIO_PME pin are capable of being driven high externally by another active device or pull-up
even when the SCH311X VCC is grounded, providing VTR power is active. The IO_PME pin driver
sinks 6mA at 0.55V max (see section 4.2.1.1 DC Specifications in the "PCI Local Bus Specification,
Revision 2.2, December 18, 1998).
The SCH311X Wake on Specific Key Code feature is enabled for the assertion of the nIO_PME signal
in SX power states by the SPEKEY bit in the
Vbat powered.
At Vbat POR the Wake on Specific Key Code feature is disabled. During the first VTR POR and VCC
POR the Wake on Specific Key Code feature remains disabled. Software selects the precise Specific
Key Code event (configuration) to wake the system and then enables the feature via the SPEKEY bit
in the
returning to or remaining in S5 sleep, the system will fully awake by a Wake on Specific Key Code
The Specific Key Code configuration and the enable for the nIO_PME are retained via Vbat POR
backed registers.
The SCH311X Wake on Specific Key Code feature is enabled for assertion of the nIO_PME signal
when in S3 power state or below by the SPEKEY bit in the
disabled and is VTR powered.
Enabling SMI Events onto the PME Pin
PME Function Pin Control
Wake on Specific Key Code
Section 12.9, "Keyboard and Mouse PME Generation," on page 136
PME_STS6
register. The system then may go the sleep and/or have a power failure. After
DATASHEET
155
GP42
PME_STS6
register. The output buffer type of the pin can be
register. This bit defaults to enabled and is
GP42
PME_EN6
register. The nIO_PME pin function
register. This bit defaults to
for information about using
Rev 0.2 (09-28-04)