SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 325

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
PME_EN7
Default = 0x00
SCH3116 DEVICE
ONLY
SP12 Option
Default = 0x44
on VTR POR
SP34 Option
Default = 0x44
on VTR POR
THIS REGISTER IS
RESERVED FOR
SCH3112 DEVICE
on Vbat POR
NAME
Table 26.3 Detailed Runtime Register Description (continued)
10
(R/W)
0x12
(R/W)
0x13
(R/W)
OFFSET
(HEX)
REG
PME Wake Enable Register 1
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”),
if the source asserts a wake event so that the associated status bit is “1”
and the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] RI3
Bit[1] RI4
Bit[2] RI5
Bit[3] RI6
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
SP Options for SP1 and SP2
Bit[0] Automatic Direction Control Select SP1
1=FC on
0=FC off
Bits[1] Signal select SP1
1=nRTS control
0=nDTR control
Bits[2] Polarity SP1
0= Drive low when enabled
1= Drive 1 when enabled
Bits[3] RESERVED
Bit[4] Automatic Direction Control Select SP2
1=FC on
0=FC off
Bits[5] Signal select SP2
1=nRTS control
0=nDTR control
Bits[6] Polarity SP2
0= Drive low when enabled
1= Drive 1 when enabled
Bits[7] RESERVED
SCH3112 DEVICE
Bits[7:0] RESERVED
DATASHEET
309
DESCRIPTION
Rev 0.2 (09-28-04)