SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 170

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
EVENTS
UART-2
UART-3
UART-4
UART-5
UART-6
Hardware Monitor
Watch Dog Timer
GPIO, total 15 pins
Low-Battery
The PME function is controlled by the PME status and enable registers in the runtime registers block,
which is located at the address programmed in configuration registers 0x60 and 0x61 in Logical
There are four types of registers which control PME events:
1. PME Wake Status register (PME_STS1, PME_STS3, PME_STS5, PME_STS6.) provides the
2. PME Wake Enable (PME_EN1, PME_EN3, PME_EN5, PME_EN6) provides the enable for
3. PME Pin Enable Register (PME_EN,) provides an enable for the PME output pins.
4. PME Pin Status Register (PME_STS) provides the status for the PME output pins.
See
The following describes the behavior to the PME status bits for each event:
Each wake source has a bit in a PME Wake Status register which indicates that a wake source has
occurred. The PME Wake Status bits are “sticky“(unless otherwise stated in bit description in
Chapter 26, "Runtime Register," on page
will remains set until cleared by writing a ‘1’ to the bit.
Each PME Wake Status register has a corresponding PME Wake Enable Register.
by nRI2 pin
by nRI2 pin
by nRI2 pin
by nRI2 pin
by nRI2 pin
status of individual wake events.
individual wake events.
Chapter 26, "Runtime Register," on page 293
by IRQ
by IRQ
by IRQ
by IRQ
by IRQ
Table 15.2 PME Events (continued)
PME
Y (from group SMI)
Y
Y (from group SMI)
Y
Y (from group SMI)
Y
Y (from group SMI)
Y
Y (from group SMI)
Y
Y
Y
Y
DATASHEET
nHWM_INT
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
293): once a status bit is set by the wake-up event, the bit
154
for detailed register description
COMMENT
Detect on VCC POR only not a
S3 wakeup either
SMSC SCH311X
Datasheet