SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 277

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
24.2.49
24.2.50
24.2.51
Address
Address
Regis-
Regis-
Register
Address
A6h
A7h
ter
ter
ABh
Read/
Read/
R/WC
R/WC
Write
Write
Read/
Write
R/W
Note: Only the primary status registers generate an interrupt event.
Register A6h: Interrupt Status Register 2 - Secondary
Notes:
■
■
See definition of
Note: Only the primary status registers generate an interrupt event.
Register A7h: Interrupt Status Register 3 - Secondary
Notes:
■
■
See definition of
Note: Only the primary status registers generate an interrupt event.
Register ABh: TACH 1-3 Mode Register
The following defines the mode control bits:
■
■
■
■
For bits[7:2], these bits are defined as follows:
This register is reset to its default value when the PWRGD_PS signal transitions high.
This is a read/write-to-clear register. The status bits in this register are cleared on a write of one if
the event causing the interrupt is no longer active. Writing a zero to these bits has no effect.
This register is reset to its default value when the PWRGD_PS signal transitions high.
This is a read/write-to-clear register. The status bits in this register are cleared on a write of one if
the event causing the interrupt is no longer active. Writing a zero to these bits has no effect.
bits[7:6]: Tach1 Mode
bits[5:4]: Tach2 Mode.
bits[3:2]: Tach3 Mode.
bits[1:0]: RESERVED.
00=normal operation (default)
01=locked rotor mode, active high signal
10=locked rotor mode, active low signal
11=undefined.
Interrupt Status Register
Interrupt Status Register
Register Name
Register Name
2 - Secondary
3- Secondary
Register Name
Tach 1-3 Mode
Register 42h: Interrupt Status Register 2 on page 238
Register 83h: Interrupt Status Register 3 on page 256
(MSb)
(MSb)
ERR2
Bit 7
Bit 7
RES
(MSb)
T1M1
Bit 7
DATASHEET
ERR1
Bit 6
Bit 6
RES
T1M0
Bit 6
261
Bit 5
Bit 5
RES
RES
T2M1
Bit 5
FANTA
Bit 4
CH3
Bit 4
RES
T2M0
Bit 4
FANTA
Bit 3
Bit 3
CH2
RES
T3M1
Bit 3
FANTA
Bit 2
Bit 2
CH1
RES
T3M0
Bit 2
for setting and clearing bits.
for setting and clearing bits.
VBAT
Bit 1
RES
Bit 1
Bit 1
RES
Rev 0.2 (09-28-04)
(LSb)
Bit 0
RES
(LSb)
(LSb)
Bit 0
Bit 0
VTR
12V
Default
Default
Default
Value
Value
Value
00h
00h
00h