SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 300

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
000
001
010
100
101
011
110
111
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Note 25.11 Logical Device IRQ and DMA Operation. IRQ and DMA Enable and Disable: Any time the
FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled.
Digital Output Register (Base+2) bit D3 (DMAEN) set to “0”.
The FDC is in power down (disabled).
Serial Ports:
Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic “0”, the serial port interrupt is
disabled.
Disabling DMA Enable bit, disables DMA for UART2. Refer to the IrCC specification.
Parallel Port:
SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to “0”, IRQ is disabled.
ECP Mode:
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Keyboard Controller: Refer to the
SMSC Defined Logical Device Configuration Registers
The SMSC Specific Logical Device Configuration Registers reset to their default values only on
PCI resets generated by Vcc or VTR POR (as shown) or the PCI_RESET# signal. These registers
are not affected by soft resets.
(FROM ECR REGISTER)
For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
The DMA channel must be disabled if not used/selected by any Logical Device. Refer to Note A.
The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for
logical device 3 and 5 is 0x04. The FDC must always be assigned to DMA Channel 2.
(DMA) dmaEn from ecr register. See table.
IRQ - See table.
MODE
IRQ or DMA channel for a logical block is disabled by a register bit in that logical block,
the IRQ and/or DMA channel must be disabled. This is in addition to the IRQ and DMA
channel disabled by the Configuration Registers (Active bit or address not valid).
PRINTER
CONFIG
TEST
FIFO
ECP
RES
SPP
EPP
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
8042 Keyboard Controller Description on page 129
284
CONTROLLED BY
IRQE
IRQE
IRQE
IRQE
IRQE
IRQ
(on)
(on)
(on)
DMA CONTROLLED BY
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
SMSC SCH311X
of this spec
Datasheet