SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 380
SCH3112I-NE
Manufacturer Part Number
SCH3112I-NE
Description
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.SCH3112I-NE.pdf
(396 pages)
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Rev 0.2 (09-28-04)
29.8
29.9
NAME
t1
t
percentage errors indicated in the “Baud Rate” table in the “Serial Port” section.
NAME
t1
t2
t3
t4
t5
t6
BR
KDAT/
MDAT
is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have
KCLK/
MCLK
DESCRIPTION
Serial Port Data Bit Time
DESCRIPTION
Time from DATA transition to falling edge of CLOCK
(Receive)
Time from rising edge of CLOCK to DATA transition (Receive)
Duration of CLOCK inactive (Receive/Send)
Time to keyboard inhibit after clock 11 to ensure the keyboard
does not start another transmission (Receive)
Time from inactive to active CLOCK transition, used to time
when the auxiliary device samples DATA (Send)
Duration of CLOCK active (Receive/Send)
UART Interface Timing
Keyboard/Mouse Interface Timing
t1
TXD1, 2
Start Bit
CLK
Data
t3
1
Figure 29.26 Keyboard/Mouse Receive/Send Data Timing
t2
t6
t4
Bit 0
Start
CLK
2
Figure 29.25 Serial Port Data
t1
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Data (5-8 Bits)
364
CLK
Bit 7
9
Parity Bit Stop Bit
CLK
MIN
MIN
5
5
30
30
>0
5
10
Parity
TYP
t
TYP
BR
1
Stop (1-2 Bits)
t5
CLK
11
MAX
MAX
25
T4-5
50
50
50
25
SMSC SCH311X
UNITS
nsec
UNITS
µsec
µsec
µsec
µsec
µsec
µsec
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