SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 211

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
23.9.1
23.9.2
23.9.3
Interrupt Pin (nHWM_INT)
The nHWM_INT function is used as an interrupt output for out-of-limit temperature and/or fan errors.
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Note: If the nHWM_INT pin is not enabled the pin will be tristate if the nHWM_INT function is selected
See
events are set to enable the interrupt status bits to be set and no events are being masked.
If the internal or remote temperature reading violates the low or high temperature limits, nHWM_INT
will be forced active low (if all the corresponding enable bits are set: individual enable bits (D1_EN,
D2_EN, and/or AMB_EN), group enable bit (TEMP_EN) and the global enable bit (INTEN)). This pin
will remain low while the Internal Temp Error bit or one or both of the Remote Temp Error bits in
Interrupt Status 1 Register is set and the corresponding enable bit(s) are set.
The nHWM_INT pin will not become active low as a result of the remote diode fault bits becoming set.
However, the occurrence of a fault will cause 80h to be loaded into the associated reading register,
which will cause the corresponding diode error bit to be set. This will cause the nHWM_INT pin to
become active if enabled.
The nHWM_INT pin can be enabled to indicate fan errors. Bit[0] of the Interrupt Enable 2 (Fan Tachs)
register (80h) is used to enable this option. This pin will remain low while the associated fan error bit
in the Interrupt Status Register 2 is set.
The nHWM_INT pin will remain low while any bit is set in any of the Interrupt Status Registers. Reading
the interrupt status registers will cause the logic to attempt to clear the status bits; however, the status
bits will not clear if the interrupt stimulus is still active. The interrupt enable bit (Special Function
Register bit[2]) should be cleared by software before reading the interrupt status registers to insure
that the nHWM_INT pin will be re-asserted while an interrupt event is active, when the INT_EN bit is
written to ‘1’ again.
The nHWM_INT pin may only become active while the monitor block is operational.
Interrupt as a PME Event
The hardware monitoring interrupt signal is routed to the SIO PME block. For a description of these
bits see the section defining PME events. This signal is unaffected by the nHWM_INT pin enable
(INT_EN) bit (See
The THERM PME status bit is located in the PME_STS1 Runtime Register at offset 04h located in the
SIO block.
When a temperature or fan tachometer event causes a status bit to be set, the THERM PME status
bits will be set as long as the corresponding group enable bit is set.
The enable bit is located in the PME_EN1 register at offset 0Ah.
Interrupt as an SMI Event
The hardware monitoring interrupt signal is routed to the SIO SMI block. For a description of these bits
see the section defining SMI events. This signal is unaffected by the nHWM_INT pin enable (INT_EN)
bit (See
The THERM SMI status bit is located in the SMI_STS5 Runtime Register at offset 14h located in the
SIO block.
When a temperature or fan tachometer event causes a status bit to be set, the THERM SMI status
bits will be set as long as the corresponding group enable bit is set.
The nHWM_INT signal is on pin 114.
To enable the interrupt pin to go active, set bit 2 of the Special Function Register (7Ch) to ‘1’.
Figure 23.3 on page
on the pin.
Figure 23.3 Interrupt Control on page
Figure 23.3 Interrupt Control on page
193. The following description assumes that the interrupt enable bits for all
DATASHEET
195
193.)
193.)
Rev 0.2 (09-28-04)