SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 57

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
DIGITAL OUTPUT REGISTER
Bit 1
0
0
1
1
RESET
COND.
Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.
DATA RATE SELECT REGISTER (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program the data rate, amount of write precompensation, power
down status, and software reset. The data rate is programmed using the Configuration Control
Register (CCR) not the DSR, for PC/AT and PS/2 Model 30.
This register is write only. It is used to program the data rate, amount of write precompensation, power
down status, and software reset. The data rate is programmed using the Configuration Control
Register (CCR) not the DSR, for PC/AT and PS/2 Model 30.
Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most
recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset
will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps.
Bit 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See
to the individual data rates. The data rate select bits are unaffected by a software reset, and are set
to 250 Kbps after a hardware reset.
Bit 2 through 4 PRECOMPENSATION SELECT
These three bits select the value of write precompensation that will be applied to the WDATA output
signal.
0 is the default starting track number to start precompensation. This starting track number can be
changed by the configure command.
7
S/W
RESET
0
Table 7.5
Bit 0
0
1
0
1
6
POWER
DOWN
0
shows the precompensation values for the combination of these bits settings. Track
5
0
0
Table 7.4 Drive Type ID
DATASHEET
REGISTER 3F3 – DRIVE TYPE ID
Bit 5
L0-CRF2 – B1
L0-CRF2 – B3
L0-CRF2 – B5
L0-CRF2 – B7
4
PRE-
COMP2
0
41
3
PRE-
COMP1
0
Table 7.6
2
PRE-
COMP0
0
Bit 4
L0-CRF2 – B0
L0-CRF2 – B2
L0-CRF2 – B4
L0-CRF2 – B6
for the settings corresponding
1
DRATE
SEL1
1
Rev 0.2 (09-28-04)
0
DRATE
SEL0
0