SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 187

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
APPLICATION NOTE: The 32.768 kHz trickle input must be connected to supply the clock signal for the nFPRST
SMSC SCH311X
20.1
20.2
The nIO_PME signal can be used to control the state of the power supply. The nIO_PME signal will
be asserted when a PME event occurs and the PME logic is enabled. The following is a summary of
the Power control PME events (See
1. PB_IN# input signal assertion. (SCH3112, SCH3114 devices only)
2. When the Wake On Specific Key Logic detects the programmed keyboard event it will generate a
3. Upon returning from a power failure.
Each PME wake event sets a status bit in the PME_STS6 register. If the corresponding enable bit in
the PME_EN6 register is set then the nIO_PME pin will be asserted. The enable bits in the PME_EN6
register default to set and are Vbat powered. Refer to
description of the PME support for this PME event.
The inputs, PWRGD_PS and nFPRST have hysteresis and are internally pulled to VTR through a 30uA
resistor. The nFPRST is debounced internally.
The nFPRST input has internal debounce circuitry that is valid on both edges for at least 16ms before
the output is changed. The 32.768kHz is used to meet the timing requirement. See
nFPRST debounce timing.
Note: The actual minimum debounce time is 15.8msec
The 32.768 kHz trickle input must be connected to supply the clock signal for the nFPRST debounce
circuitry. The SCH311X has a legacy feature which is incompatible with use of the nFPRST input
signal. An internal 32kHz clock source derived from the 14MHz (VCC powered) can be selected when
the external 32kHz clock is not connected.
nIO_PME Pin use in Power Control
Front Panel Reset
nFPRST
in the 8-bit shift register, which is stored in the PS_ON register located in the Runtime Register
block at 4Ah. The bit selected in mode 2 is determined by the the state of the PS_ON# Previous
State Select bits located in Runtime Register 53h.
wake event (KB_PB_STS).
0
0
1
1
debounce circuitry.
INPUTS
Table 20.2 Internal PWROK Truth Table
DATASHEET
Figure
PWRGD_PS
171
0
1
0
1
20.1):
Chapter 15, "PME Support," on page 153
INTERNAL
OUTPUT
PWROK
0
0
0
1
Rev 0.2 (09-28-04)
Figure 20.2
for
for