SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 41

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Chapter 4 Power Functionality
SMSC SCH311X
4.1
4.2
4.3
4.4
TheSCH311X has five power planes: VCC, HVTR, VREF, VTR, and Vbat.
The SCH311X is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). VCC is the main power supply
for the Super I/O Block. See
The SCH311X is family of 3.3 Volt devices. The HVTR supply is 3.3 Volts (nominal). HVTR is a
dedicated power supply for the Hardware Monitoring Block. HVTR is connected to the VTR suspend
well. See
Note: The hardware monitoring logic is powered by HVTR, but only operational when VCC is on. The
The SCH311X is a 3.3-Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V
tolerant; that is, the operating input voltage is 5.5V Max, and the I/O buffer output pads are backdrive
protected (they do not impose a load on any external VCC powered circuitry). The 5V tolerant pins are
applicable to the Super I/O Block only.
The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling.
These pins are:
■
■
■
The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the
following pins in the Super I/O Block:
■
■
■
■
The Hardware Monitoring Block digital pins are 3.3V only.
The SCH311X requires a trickle supply (VTR) to provide sleep current for the programmable wake-up
events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See
Chapter 28, "Operational Description," on page
depends on the functions that are used in the part. See
page
If the SCH311X is not intended to provide wake-up capabilities on standby current, VTR can be
connected to VCC. VTR powers the IR interface, the PME configuration registers, and the PME
interface. The VTR pin generates a VTR Power-on-Reset signal to initialize these components. If VTR
is to be used for programmable wake-up events when VCC is removed, VTR must be at its full
VCC Power
HVTR Power
3 Volt Operation / 5 Volt Tolerance
VTR Support
LAD[3:0]
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
nIO_PME
339.
hardware monitoring block is connected to the suspend well to retain the programmed
configuration through a sleep cycle.
Section 28.2, "DC Electrical Characteristics," on page
Section 28.2, "DC Electrical Characteristics," on page
DATASHEET
25
339. The maximum VTR current that is required
Chapter 28, "Operational Description," on
339.
339.
Rev 0.2 (09-28-04)