SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 274

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
24.2.39
24.2.40
Register
Address
Register
Address
8Eh
90h
91h
92h
/Write
Read
/Write
Read
R/W
R/W
R/W
R
This register must not be written. Writing this register may produce unexpected results.
Registers 8Eh: SMSC Test Register
This register is an SMSC Test register.
Registers 90h-92h: FANTACHX Option Registers
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
Bit[0] SLOW
0= Force tach reading register to FFFFh if number of tach edges detected is greater than 0, but less
than programmed number of edges. (default)
1=Force tach reading register to FFFEh if number of tach edges detected is greater than 0, but less
than programmed number of edges.
Bit[2:1] The number of edges for tach reading:
00=2 edges
01=3 edges
10=5 edges (default)
11=9 edges
Bit[3] Tachometer Reading Mode
0=mode 1 standard (Default)
1=mode 2 enhanced.
Notes:
■
■
Bit[4] 3 Edge Detection (Mode 2 only)
0=Don’t ignore first 3 edges (default)
1=Ignore first 3 tachometer edges after guard time
Note: This bit has been added to support a small sampling of fans that emit irregular tach pulses
Unused FANTACH inputs must be configured for Mode 1.
Tach inputs associated with PWM outputs that are configured for high frequency mode must be
configured for Mode 1.
when the PWM transitions ‘ON’. Typically, the guard time is sufficient for most fans.
FANTACH1 Option
FANTACH2 Option
FANTACH3 Option
Register Name
SMSC Test Register
Register Name
(MSb)
Bit 7
RES
RES
RES
(MSb)
TST7
Bit 7
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Bit 6
RES
RES
RES
258
TST6
Bit 6
Bit 5
RES
RES
RES
TST5
Bit 5
3EDG
3EDG
3EDG
Bit 4
TST4
Bit 4
MODE
MODE
MODE
Bit 3
TST3
Bit 3
EDG1
EDG1
EDG1
Bit 2
TST2
Bit 2
EDG0
EDG0
EDG0
Bit 1
TST1
Bit 1
SLOW
SLOW
SLOW
(LSb)
SMSC SCH311X
(LSb)
Bit 0
TST0
Bit 0
Datasheet
Default
Default
Value
Value
N/A
04h
04h
04h