SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 326

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
SP34 Option
Default = 0x44
on VTR POR
SCH3114 AND
SCH3116 DEVICE
ONLY.
SMI_STS1
Default = 0x02, or
0x03 On VTR POR.
The default will be
0x03 if there is a
LOW_BAT event
under VBAT power
only, or 0x02 if this
event does not
occur. Bit 0 will be
set to ‘1’ on a VCC
POR if the battery
voltage drops below
2.4V under VTR
power (VCC=0) or
under battery power
only.
Bit 1 is set to ‘1’ on
VCC POR, VTR
POR, PCI Reset
and soft reset.
SMI_STS2
Default = 0x00
on VTR POR
NAME
Table 26.3 Detailed Runtime Register Description (continued)
0x13
(R/W)
14
Bits[0] are
R/WC.
Bits[1:4,7]
are RO.
15
(R/W)
Bits[0,1] are
RO
Bits[2] is
Read-Clear.
OFFSET
(HEX)
REG
SCH3114 AND SCH3116 DEVICE SP Options for SP3 and SP4
Bit[0] Automatic Direction Control Select SP3
1=FC on
0=FC off
Bits[1] Signal select SP3
1=nRTS control
0=nDTR control
Bits[2] Polarity SP3
0= Drive low when enabled
1= Drive 1 when enabled
Bits[3] RESERVED
Bit[4] Automatic Direction Control Select SP4
1=FC on
0=FC off
Bits[5] Signal select SP4
1=nRTS control
0=nDTR control
Bits[6] Polarity SP4
0= Drive low when enabled
1= Drive 1 when enabled
Bits[7] RESERVED
SMI Status Register 1
This register is used to read the status of the SMI inputs.
The following bits must be cleared at their source except as shown.
Bit[0] LOW_BAT. Cleared by a write of ‘1’. When the battery is removed
and replaced or if the battery voltage drops below 1.2V (nominal) under
battery power only (VBAT POR), then the LOW_BAT SMI status bit is set
on VTR POR. When the battery voltage drops below 2.4 volts (nominal)
under VTR power (VCC=0) or under battery power only, the LOW_BAT
SMI status bit is set on VCC POR.
Bit[1] PINT. The parallel port interrupt defaults to ‘1’ when the parallel port
activate bit is cleared. When the parallel port is activated, PINT follows the
nACK input.
Bit[2] U2INT
Bit[3] U1INT
Bit[4] FINT
Bit[5] Reserved
Bit[6] Reserved
Bit[7] WDT
SMI Status Register 2
This register is used to read the status of the SMI inputs.
Bit[0] MINT. Cleared at source.
Bit[1] KINT. Cleared at source.
Bit[2] IRINT. This bit is set by a transition on the IR pin (IRRX). Cleared
by a read of this register.
Bit[3] Reserved
Bit[4] SPEMSE_STS (Wake on specific mouse click) - Cleared by writing a
‘1’
Bit[7:5] Reserved
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
310
DESCRIPTION
SMSC SCH311X
Datasheet