SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 319

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
26.2
PME_STS
Default = 0x00
on VTR POR
PME_EN
Default = 0x00
on VTR POR
PME_STS1
Default = 0x00
on VTR POR
NAME
Note 26.14 Bit 0 is not cleared by PCI RESET.
Note 26.15 This register contains some bits that are read or write only.
Note 26.16 See the register description for the bit-wise access type.
Note 26.17 This register is read/write when Bit [7] in the
The following registers are located at an offset from (PME_BLK) the address programmed into the
base I/O address register for Logical Device A.
Runtime Register Description
Read-Only when Bit [7] is set to '1'.
00
(R/WC)
02
(R/W)
04
(R/WC)
OFFSET
(HEX)
REG
Table 26.3 Detailed Runtime Register Description
PME Pin Status Register
Bit[0] PME_Status
= 0
= 1 Autonomously Set when a wakeup event occurs that normally asserts
the nIO_PME signal. This bit is set independent of the state of the
PME_EN bit
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET or PCI RESET.
Writing a “1” to PME_Status will clear it and cause the device to stop
asserting nIO_PME, in enabled. Writing a “0” to PME_Status has no effect.
PME Pin Enable Register
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or PCI RESET
PME Wake Status Register 1
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] HW_Monitor
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] Reserved
Bit[6] IRINT. This bit is set by a transition on the IR pin (IRRX)
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
(default)
nIO_PME signal assertion is disabled (default)
Enables this device to assert nIO_PME signal
DATASHEET
303
Mouse_Specific_Wake
DESCRIPTION
Register is set to '0' and
Rev 0.2 (09-28-04)