SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 253

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
Bit[7] INT2
This bit indicates that a status bit is set in the Interrupt Status Register 2 Register. Therefore, S/W
can poll this register, and only if bit 7 is set does the other registers need to be read. This bit is cleared
(set to 0) automatically by the device if there are no bits set in the Interrupt Status Register 2.
Bits[6:0] Individual Status Bits
Bits[6:0] of the Interrupt Status Register 1 are automatically set by the device whenever the measured
temperature on Remote Diode 1, Internal Diode, or the Remote Diode 2 Temperature violates the limits
set in the corresponding temperature limit registers. These individual status bits remain set until the bit
is written to one by software or until the individual enable bit is cleared, even if the temperatures no
longer violate the limits set in the limit registers.
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Notes:
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Clearing the status bits by a write of ‘1’
The voltage status bits are cleared (set to 0) automatically by the SCH311X after they are written
to one by software, if the voltage readings no longer violate the limit set in the limit registers. See
Registers 44-4Dh, 9B-9Eh: Voltage Limit Registers on page
The temperature status bits are cleared (set to 0) automatically by the SCH311X after they are
written to one by software, if the temperature readings no longer violate the limit set in the limit
registers. See
Clearing the status bits by clearing the individual enable bits.
Clearing or setting the individual enable bits does not take effect unless the START bit is 1. No
interrupt status events can be generated when START=0 or when the individual enable bit is
cleared. If the status bit is one and the START bit is one then clearing the individual enable bit will
immediately clear the status bit. If the status bit is one and the START bit is zero then clearing the
individual enable bit will have no effect on the status bit until the START bit is set to one. Setting
the START bit to one when the individual enable bit is zero will clear the status bit. Setting or
clearing the START bit when the individual enable bit is one has no effect on the status bits.
The individual enable bits for D2, AMB, and D1 are located in the Interrupt Enable 3 (Temp) register
at offset 82h.
Clearing the group Temp enable bit or the global INTEN enable bit has no effect on the status bits.
Registers 4E-53h: Temperature Limit Registers on page
DATASHEET
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Rev 0.2 (09-28-04)