SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 321

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
PME_STS6
Default = 0x00 or
0x01 on VTR POR
The default will be
0x01 if there is a
LOW_BAT event
under VBAT power
only, 0x00 if the
event does not
occurs.
Bit[0] will be set to
‘1’ on a VCC POR if
the battery voltage
drops below 2.4V
under VTR power
(VCC=0) or under
battery power only.
SCH3116 DEVICE
ONLY
PME_EN1
Default = 0x00
on VTR POR
NAME
Table 26.3 Detailed Runtime Register Description (continued)
07
(R/WC)
08
(R/W)
OFFSET
(HEX)
REG
This register indicates the state of the individual PME sources, independent
of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] LOW_BAT, Cleared by a write of ‘1’.
When the battery is removed and replaced or the if the battery voltage
drops below 1.2V under battery power, then the LOW_BAT PME status bit
is set on VTR POR. When the battery voltage drops below 2.4 volts under
VTR power (VCC=0) or under battery power only, the LOW_BAT PME
status bit is set on VCC POR. The corresponding enable bit must be set
to generate a PME. The low battery event is not a PME wakeup event.
Bit[1] RESERVED.
Bit[2] GP60
Bit[3] GP61
Bit[4] SPEMSE_STS (Wake on specific mouse click)
Bit[5] SPEKEY_STS (Wake on specific key)
Bit[6] PB_STS
Bit[7] Reserved
The PME Status register is not affected by VCC POR, SOFT RESET or
PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Status
Register has no effect.
PME Wake Enable Register 1
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”),
if the source asserts a wake event so that the associated status bit is “1”
and the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] HW_Monitor
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] Reserved
Bit[6] IRINT
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
DATASHEET
305
DESCRIPTION
Rev 0.2 (09-28-04)