SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 153

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Caution:
USER’S NOTE: Regarding External Keyboard and Mouse:
SMSC SCH311X
Bit 6 of configuration register 0x2C is used to put the 8042 into reset - do not set any of the other bits
in register 0x2C, as this may produce undesired results.
The bits used to isolate the keyboard and mouse signals from the 8042 are located in Logical Device
7, Register 0xF0 (KRST_GA20) and are defined below. These bits reset on VTR POR only.
Bit[6]
1 = block mouse clock and data signals into 8042
0 = do not block mouse clock and data signals into 8042
Bit[5]
1 = block keyboard clock and data signals into 8042
0 = do not block keyboard clock and data signals into 8042
When the keyboard and/or mouse isolation bits are used, it may be necessary to reset the 8042 upon
exiting the sleep state. If either of the isolation bits is set prior to entering a sleep state where VCC
goes inactive (S3-S5), then the 8042 must be reset upon exiting the sleep mode. Write 0x40 to global
configuration register 0x2C to reset the 8042. The 8042 must then be taken out of reset by writing
0x00 to register 0x2C since the bit that resets the 8042 is not self-clearing.
It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does
not go inactive (S1, S2).
This is an application matter resulting from the behavior of the external 8042 in the keyboard.
When the external keyboard and external mouse are powered up, the KDAT and MDAT lines are driven
low. This sets the KBD bit (D3) and the MOUSE bit (D4) of the PME Wake Status Register since the
KDAT and MDAT signals cannot be isolated internal to the part. This causes an nIO_PME assertion
to be generated if the keyboard and/or mouse PME events are enabled. Note that the keyboard and
mouse isolation bits only prevent the internal 8042 in the part from setting these status bits.
Case 1: Keyboard and/or Mouse Powered by VTR
The KBD and/or MOUSE status bits will be set upon a VTR POR if the keyboard and/or mouse are
powered by VTR.
In this case, a nIO_PME will not be generated, since the keyboard and mouse PME enable bits are
reset to zero on a VTR POR. The BIOS software needs to clear these PME status bits after power-up.
In this case, an nIO_PME will be generated if the enable bits were set for wakeup, since the keyboard
and mouse PME enable bits are Bvat powered. Therefore, if the keyboard and mouse are powered
by VTR, the enable bits for keyboard and mouse events should be cleared prior to entering a sleep
state where VTR is removed (i.e., S4 or S5) to prevent a false PME from being generated. In this case,
the keyboard and mouse should only be used as PME and/or wake events from the power states S3
or below.
Case 2: Keyboard and/or Mouse Powered by VCC
The KBD and/or MOUSE status bits will be set upon a VCC POR if the keyboard and/or mouse are
powered by VCC. In this case, a nIO_PME and a nIO_PME will be generated if the enable bits were
set for wakeup, since the keyboard and mouse PME enable bits are VTRor Vbat powered. Therefore,
if the keyboard and mouse are powered by VCC, the enable bits for keyboard and mouse events
should be cleared prior to entering a sleep state where VCC is removed (i.e., S3) to prevent a false
PME from being generated. In this case, the keyboard and mouse should only be used as PME and/or
wake events from the S0 and/or S1 states. The BIOS software needs to clear these PME status bits
after power-up.
M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT
signal to The mouse wakeup (PME) logic.
K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT
signal to the keyboard wakeup (PME) logic.
DATASHEET
137
Rev 0.2 (09-28-04)