SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 324

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
PME_STS7
Default = 0x00
SCH3116 DEVICE
ONLY
PME_EN7
Default = 0x00
SCH3112 DEVICE
ONLY
PME_EN7
Default = 0x00
SCH3114 DEVICE
ONLY
on VTR POR
on Vbat POR
on Vbat POR
NAME
Table 26.3 Detailed Runtime Register Description (continued)
0C
(R/WC)
10
(R/W)
10
(R/W)
OFFSET
(HEX)
REG
PME Wake Status Register 7
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] RI3
Bit[1] RI4
Bit[2] RI5
Bit[3] RI6
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
RESERVED
Bit[7:0] Reserved
PME Wake Enable Register 1
This register is used to enable individual PME wake sources onto the
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”),
if the source asserts a wake event so that the associated status bit is “1”
and the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] RI3
Bit[1] RI4
Bit[2] Reserved
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
308
DESCRIPTION
SMSC SCH311X
Datasheet