SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 129

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
Bit 5 DIRECTION
If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state
of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output
mode (write); a logic 1 means that the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be written.
cFifo (Parallel Port Data FIFO)
ADDRESS OFFSET = 400h
Mode = 010
Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the
peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode
is only defined for the forward direction.
ecpDFifo (ECP Data FIFO)
ADDRESS OFFSET = 400H
Mode = 011
Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by
a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO
are byte aligned.
Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO
when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system.
tFifo (Test FIFO Mode)
ADDRESS OFFSET = 400H
Mode = 110
Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data
in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol
handshake. However, data in the tFIFO may be displayed on the parallel port data lines.
The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full
tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty
tFIFO, the last data byte is re-read again. The full and empty bits must always keep track of the correct
FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate
performance metrics.
The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking
the full and serviceIntr bits.
The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and
emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will
indicate that the threshold has been reached.
The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO
a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that
the threshold has been reached.
Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For
example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the
same order as was written.
DATASHEET
113
Rev 0.2 (09-28-04)