SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 125

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16 byte FIFO.
3. The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration Registers.
NAME
nStrobe
PData 7:0
nAck
PeriphAck (Busy)
ecpDFifo
cnfgA
cnfgB
tFifo
ecr
ECP IMPLEMENTATION STANDARD
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC
devices supporting ECP must meet the requirements contained in this section or the port will not be
supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended
Capabilities Port Protocol and ISA Interface Standard , Rev. 1.14 , July 14, 1993. This document is
available from Microsoft.
Description
The port is software and hardware compatible with existing parallel ports so that it may be used as a
standard LPT port if ECP is not required. The port is designed to be simple and requires a small
number of gates to implement. It does not do any “protocol” negotiation, rather it provides an automatic
high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions.
Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve
the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an
automatic handshake for the standard parallel port to improve compatibility mode transfer speed.
The port also supports run length encoded (RLE) decompression (required) in hardware. Compression
is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many
times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the
following byte the specified number of times. Hardware support for compression is optional.
D7
compress
0
TYPE
O
I/O
I
I
D6
intrValue
MODE
0
DESCRIPTION
During write operations nStrobe registers data or address into the slave on the
asserting edge (handshakes with Busy).
Contains address or data or RLE data.
Indicates valid data driven by the peripheral when asserted. This signal
handshakes with nAutoFd in reverse.
This signal deasserts to indicate that the peripheral can accept data. This
signal handshakes with nStrobe in the forward direction. In the reverse
direction this signal indicates whether the data lines contain ECP command
information or data. The peripheral uses this signal to automatic direction
control in the forward direction. It is an “interlocked” handshake with nStrobe.
PeriphAck also provides command information in the reverse direction.
Table 9.3 ECP Pin Descriptions
D5
0
Parallel Port IRQ
DATASHEET
ECP Data FIFO
D4
nErrIntrE
Test FIFO
109
1
n
D3
dmaEn
0
D2
service
Intr
0
Parallel Port DMA
D1
full
0
D0
empty
Rev 0.2 (09-28-04)
0
NOTE
2
2