SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 70

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
SYMBOL
SK
SRT
ST0
ST1
ST2
ST3
WGATE
NAME
Skip Flag
Step Rate
Interval
Status 0
Status 1
Status 2
Status 3
Write Gate
Table 7.14 Description of Command Symbols (continued)
DESCRIPTION
When set to 1, sectors containing a deleted data address mark will
automatically be skipped during the execution of Read Data. If Read Deleted is
executed, only sectors with a deleted address mark will be accessed. When
set to “0”, the sector is read or written the same as the read and write
commands.
The time interval between step pulses issued by the FDC. Programmable from
0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to
the SPECIFY command for actual delays.
Registers within the FDC which store status information after a command has
been executed. This status information is available to the host during the result
phase after command execution.
Alters timing of WE to allow for pre-erase loads in perpendicular drives.
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
54
SMSC SCH311X
Datasheet