SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 141

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Chapter 11 Serial IRQ
SMSC SCH311X
PCI_CLK
SER_IRQ
PCI_CLK
SER_IRQ
Drive Source
Driver
The SCH311X supports the serial interrupt to transmit interrupt information to the host system. The
serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
TIMING DIAGRAMS FOR SER_IRQ CYCLE
a. Start Frame timing with source sampled a low pulse on IRQ1
Notes:
1. H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
2. Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge
b. Stop Frame Timing with Host using 17 SER_IRQ sampling period
Notes:
1. H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
2. The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-
3. There may be none, one or more Idle states during the Stop Frame.
4. Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
SER_IRQ CYCLE CONTROL
There are two modes of operation for the SER_IRQ Start Frame
1. Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one
hierarchy in a synchronous bridge design.
around clock of the Stop Frame.
clock, while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately
be tri-stated without at any time driving high. A Start Frame may not be initiated while the
SER_IRQ is Active. The SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active
between Start and Stop Frames. This mode of operation allows the SER_IRQ to be Idle when there
are no IRQ/Data transitions which should be most of the time.
S
FRAME
None
IRQ14
R
IRQ1
SL
or
H
T
START
S
Host Controller
IRQ15
START FRAME
H
IRQ15
FRAME
R
1
T
DATASHEET
R
S
IOCHCK#
None
FRAME
125
R
T
IRQ0 FRAME IRQ1 FRAME
T
S
None
I
R
2
STOP FRAME
Host Controller
T
STOP
H
S
IRQ1
1
R
R
T
T
NEXT CYCLE
IRQ2 FRAME
S
None
START
Rev 0.2 (09-28-04)
R
T
3