SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 323
SCH3112I-NE
Manufacturer Part Number
SCH3112I-NE
Description
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.SCH3112I-NE.pdf
(396 pages)
- Current page: 323 of 396
- Download datasheet (6Mb)
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
PME_EN6
Default = 0x00 on
VTR POR
SCH3116 DEVICE
ONLY
NOTE: Bit 7 of this
register needs to be
VBAT powered
PME_STS7
Default = 0x00
SCH3112 DEVICE
ONLY
PME_STS7
Default = 0x00
SCH3114 DEVICE
ONLY
on VTR POR
on VTR POR
NAME
Table 26.3 Detailed Runtime Register Description (continued)
0B
(R/W)
0C
(R/WC)
0C
(R/WC)
OFFSET
(HEX)
REG
PME Enable Register 6
This register is used to enable individual PME sources onto the nIO_PME
signal.
When the PME Enable register bit for a PME source is active (“1”), if the
source asserts a PME event and the PME_EN bit is “1”, the source will
assert the nIO_PME signal.
When the PME Enable register bit for a PME source is inactive (“0”), the
PME Status register will indicate the state of the PME source but will not
assert the nIO_PME signal.
Bit[0] LOW_BAT
Bit[1] Reserved
Bit[2] GP60
Bit[3] GP61
Bit[4] SPEMSE_EN (Wake on specific mouse click)
Bit[5] SPEKEY_EN (Wake on specific key)
Bit[6] PB_EN
Bit[7] Reserved
The PME Enable register 6 is not affected by VCC POR, SOFT RESET or
PCI RESET.
RESERVED
Bit[7:0] Reserved
PME Wake Status Register 7
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] RI3
Bit[1] RI4
Bit[2] Reserved
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
DATASHEET
307
DESCRIPTION
Rev 0.2 (09-28-04)
Related parts for SCH3112I-NE
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
(SCH3112 - SCH3116) LPC IO
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
FAST ETHERNET PHYSICAL LAYER DEVICE
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
4-PORT USB2.0 HUB CONTROLLER
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
FDC37C672ENHANCED SUPER I/O CONTROLLER WITH FAST IR
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
COM90C66LJPARCNET Controller/Transceiver with AT Interface and On-Chip RAM
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet: