SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 305

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
Serial Port 3
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
SCH3112 device.
Serial Port 3
Mode Register
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
SCH3114 and the
SCH3116 device.
Security Key Control
(SKC) Register
Default=0x04 on a VTR
POR, VCC POR, PCI
Reset
NAME
NAME
Table 25.16 Serial Port 3, Logical Device B [Logical Device Number = 0X0B
Note: The registers located in Logical Device A are runtime registers.
Table 25.15 Logical Device A [Logical Device Number = 0X0A] (continued)
when bit[0]=1
REG INDEX
Read-Only
R/W when
REG INDEX
bit[0]= 0
0xF0 R/W
0xF0 R/W
0xF2
Bit[0] SKC Register Lock
This bit blocks write access to the Security Key Control Register.
0 = Security Key Control Register is a Read/Write register (default)
1 = Security Key Control Register is a Read-Only register
Bit[1] Read-Lock
This bit prevents reads from the Security Key registers located at an
offset from the Secondary Base I/O address in Logical Device A
0 = Permits read operations in the Security Key block (default)
1 = Prevents read operations in the Security Key block (Reads
return 00h.)
Bit[2] Write-Lock
This bit prevents writes to the Security Key registers located at an
offset from the Secondary Base I/O address in Logical Device A
0 = Permits write operations in the Security Key block
1 = Prevents write operations in the Security Key block (default)
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
Bit[7:0] SMSC Test Bit
Must be written with zero for proper operation.
SCH 3114, SCH3116 devices
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Bit[1] High Speed
= 0 High Speed Disabled(default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[6] SMSC Test Bit
Must be written with zero for proper operation.
Bit[7]: Share IRQ
=0 UARTS 3,4 use different IRQs
=1 UARTS 3,4 share a common IRQ
(Note
DATASHEET
25.12)
289
DEFINITION
DEFINITION
Rev 0.2 (09-28-04)