SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 243

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
Addr
Reg
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
Note 2
/Write
R/WC
Read
RWC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4.4
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Interrupt Enable (Fan Tachs)
Interrupt Status 1 Secondary
A/D Converter LSbs Reg 5
A/D Converter LSbs Reg 1
A/D Converter LSbs Reg 2
A/D Converter LSbs Reg 3
A/D Converter LSbs Reg 4
Interrupt Status Register 3
Special Function Register
Interrupt Enable Voltages
TACH_PWM Association
Interrupt Enable (Temp)
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
FANTACH1 Option
FANTACH2 Option
FANTACH3 Option
VBAT Limit Low
VBAT Reading
VTR Limit Low
PWM1 Option
PWM2 Option
PWM3 Option
VBAT Limit Hi
Configuration
VTR Reading
VTR Limit Hi
Reg Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 24.1 Register Summary (continued)
Note 24.
Note 24.
Note 24.
VTR.3
RD2.3
VCC.3
SMSC
SMSC
SMSC
V12.3
V50.3
INT23
MSb
TST7
AVG2
TST7
TST7
TST7
TST7
TST7
Bit 7
RES
RES
RES
VCC
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
INIT
5
5
5
7
7
7
7
7
DATASHEET
Note 24.
Note 24.
Note 24.
Note 24.
SMSC
VTR.2
RD2.2
VCC.2
SMSC
SMSC
SMSC
V12.2
V50.2
TST 6
TST 6
TST6
AVG1
TST6
TST6
TST6
TST6
TST6
Bit 6
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
12V
D2
6
5
5
5
6
6
6
6
6
Note 24.
227
SMSC
VTR.1
RD2.1
VCC.1
SMSC
SMSC
SMSC
V12.1
V50.1
TST 5
TST 5
TST5
AVG0
TST5
TST5
TST5
TST5
TST5
Bit 5
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
OPP
OPP
OPP
RES
RES
RES
RES
AMB
T3H
5V
6
5
5
5
5
5
Note 24.
SUREN
SMSC
VTR.0
RD2.0
VCC.0
3EDG
3EDG
3EDG
GRD1
GRD1
GRD1
TST 4
TST 4
TST4
V12.0
V50.0
TST4
TST4
TST4
TST4
TST4
TST4
TST4
Bit 4
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
VTR
T3L
D1
6
4
4
4
4
4
Note 24.
Note 24.
VBAT.3
FANTA
MODE
MODE
MODE
SMSC
RD1.3
VCCP
TRDY
D2EN
V25.3
VCP.3
GRD0
GRD0
GRD0
TST3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
TST3
AM.3
Bit 3
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
CH3
T2H
5V
6
8
3
3
3
3
3
VBAT.2
FANTA
INTEN
RD1.2
D1EN
VCP.2
EDG1
EDG1
EDG1
SZEN
SZEN
SZEN
TST2
V25.2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
TST2
MON
AM.2
Bit 2
RES
RES
RES
2.5V
RES
RES
RES
RES
RES
RES
RES
RES
VCC
_DN
CH2
T2L
2
2
2
2
2
VBAT.1
UPDT1
UPDT1
UPDT1
FANTA
RD1.1
MON-
VCP.1
EDG0
EDG0
EDG0
TST1
VBAT
VBAT
V25.1
TST1
TST1
TST1
TST1
TST1
TST1
TST1
TST1
TST1
AM.1
Bit 1
RES
RES
RES
RES
AMB
RES
RES
RES
RES
RES
RES
RES
Vccp
CH1
T1H
MD
1
1
1
1
1
VBAT.0
UPDT0
UPDT0
UPDT0
RD1.0
SLOW
SLOW
SLOW
TACH
TEMP
VCP.0
TST0
VOLT
V25.0
TST0
TST0
TST0
TST0
TST0
TST0
TST0
FAN-
AM.0
TST0
TST0
Bit 0
LSb
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
2.5V
VTR
T1L
0
0
0
0
0
Note 24.7
Default
Value
ECh
00h
00h
00h
40h
00h
14h
0Eh
24h
0Eh
00h
00h
00h
00h
00h
00h
00h
4Dh
4Dh
09h
09h
N/A
00h
04h
04h
04h
00h
0Ch
0Ch
0Ch
5Ah
F1h
00h
00h
00h
FFh
00h
FFh
00h
00h
00h
00h
00h
N/A
02h
00h
Rev 0.2 (09-28-04)
Note 24
Lock
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
.4
monitor
com-
cycle
plete