SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 272

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
24.2.32
24.2.33
Register
Address
Register
Address
BIT
2-7
0
1
84h
85h
86h
87h
88h
83h
Read/
Write
VTR_Error
Vbat_Error
RWC
Reserved
Read/
Write
R
R
R
R
R
NAME
The individual thermal error event bits are defined as follows:
0=disable
1=enable.
Register 83h: Interrupt Status Register 3
Note: This is a read/write-to-clear register. The status bits are cleared on a write of one if the event
The Interrupt Status Register 3 bits[1:0] are automatically set by the device whenever a voltage event
occurs on the VTR or Vbat inputs. A voltage event occurs when any of these inputs violate the limits
set in the corresponding limit registers.
This register holds a set bit until the event is cleared by software or until the individual enable bit is
cleared. Once set, the Interrupt Status Register 3 bits remain set until the individual enable bits is
cleared, even if the voltage or tachometer reading no longer violate the limits set in the limit registers.
Note that clearing the group Temp, Fan, or Volt enable bits or the global INTEN enable bit has no
effect on the status bits.
Note: The individual enable bits for VTR and Vbat are located in the Interrupt Enable 1 register at
This register is read only – a write to this register has no effect.
Registers 84h-88h: A/D Converter LSbs Registers
1
A/D Converter LSbs Reg 5
A/D Converter LSbs Reg 1
A/D Converter LSbs Reg 2
A/D Converter LSbs Reg 3
A/D Converter LSbs Reg 4
causing the interrupt is no longer active. Writing a zero to these bits has no effect.
offset 7Eh.
Interrupt Status 3
Register
Name
Register
Name
R/W
R
R
R
DEFAULT
0
0
0
(MSb)
Bit 7
RES
VCC.3
(MSb)
VTR.3
RD2.3
V12.3
V50.3
Bit 7
DATASHEET
The device automatically sets this bit to 1 when the VTR input
voltage is less than or equal to the limit set in the VTR Low Limit
register or greater than the limit set in the VTR High Limit register.
The device automatically sets this bit to 1 when the Vbat input
voltage is less than or equal to the limit set in the Vbat Low Limit
register or greater than the limit set in the Vbat High Limit register.
Reserved
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
VTR.2
VCC.2
RD2.2
V12.2
V50.2
Bit 6
Bit 6
RES
256
VTR.1
VCC.1
RD2.1
V12.1
V50.1
Bit 5
Bit 5
RES
VTR.0
VCC.0
RD2.0
V12.0
V50.0
Bit 4
Bit 4
RES
DESCRIPTION
VBT.3
RD1.3
VCP.3
V25.3
AM.3
Bit 3
Bit 3
RES
RD1.2
VCP.2
VBT.2
V25.2
AM.2
Bit 2
Bit 2
RES
RD1.1
VCP.1
VBT.1
V25.1
AM.1
Bit 1
Bit 1
Vbat
(LSb)
RD1.0
VCP.0
Bit 0
VBT.0
VTR
(LSb)
V25.0
SMSC SCH311X
AM.0
Bit 0
Datasheet
Default
Default
Value
Value
00h
N/A
N/A
N/A
N/A
N/A