SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 320

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
PME_STS3
Default = 0x00
PME_STS5
Default = 0x00
PME_STS6
Default = 0x00 or
0x01 on VTR POR
The default will be
0x01 if there is a
LOW_BAT event
under VBAT power
only, 0x00 if the
event does not
occurs.
Bit[0] will be set to
‘1’ on a VCC POR if
the battery voltage
drops below 2.4V
under VTR power
(VCC=0) or under
battery power only.
SCH3112, SCH3114
DEVICES
on VTR POR
on VTR POR
NAME
Table 26.3 Detailed Runtime Register Description (continued)
05
(R/WC)
06
(R/WC)
07
(R/WC)
OFFSET
(HEX)
REG
PME Wake Status Register 3
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] WDT
Bit[1] GP21
Bit[2] GP22
Bit[3] DEVINT_STS (status of group SMI signal for PME)
Bit[4] GP27
Bit[5] GP32
Bit[6] GP33
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
PME Wake Status Register 5
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
This register indicates the state of the individual PME sources, independent
of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] LOW_BAT, Cleared by a write of ‘1’.
When the battery is removed and replaced or the if the battery voltage
drops below 1.2V under battery power, then the LOW_BAT PME status bit
is set on VTR POR. When the battery voltage drops below 2.4 volts under
VTR power (VCC=0) or under battery power only, the LOW_BAT PME
status bit is set on VCC POR. The corresponding enable bit must be set
to generate a PME. The low battery event is not a PME wakeup event.
Bit[1] RESERVED.
Bit[2] GP60
Bit[3] GP61
Bit[4] SPEMSE_STS (Wake on specific mouse click)
Bit[5] SPEKEY_STS (Wake on specific key)
Bit[6] PB_STS
Bit[7] PFR_STS Power Failure Recovery Status
The PME Status register is not affected by VCC POR, SOFT RESET or
PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Status
Register has no effect.
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
304
DESCRIPTION
SMSC SCH311X
Datasheet