SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 51

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Chapter 7 Floppy Disk Controller
SMSC SCH311X
7.1
7.1.1
PRIMARY
ADDRESS
3F0
3F1
3F2
3F3
3F4
3F4
3F5
3F6
3F7
3F7
RESET
COND.
7
INT
PENDING
0
The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy
disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write
Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS
765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and
underflow protection. SCH311X supports a single floppy disk drive.
The FDC is compatible to the 82077AA using SMSC’s proprietary floppy disk controller core.
The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the
host microprocessor and the disk drive.
registers. Registers other than the ones shown are not supported. The rest of the description assumes
that the primary addresses have been selected.
(Shown with base addresses of 3F0 and 370)
Status Register A (SRA)
Address 3F0 READ ONLY
This register is read-only and monitors the state of the internal interrupt signal and several disk
interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2
mode. In the PC/AT mode the data bus pins D0 – D7 are held in a high impedance state for a read
of address 3F0.
PS/2 MODE
FDC Internal Registers
SECONDARY
ADDRESS
370
371
372
373
374
374
375
376
377
377
6
nDRV2
1
Table 7.1 Status, Data and Control Registers
5
STEP
0
R/W
R
R
R/W
R/W
R
W
R/W
R
W
DATASHEET
4
nTRK0
N/A
Table 7.1
35
REGISTER
Status Register A (SRA)
Status Register B (SRB)
Digital Output Register (DOR)
Tape Drive Register (TDR)
Main Status Register (MSR)
Data Rate Select Register (DSR)
Data (FIFO)
Reserved
Digital Input Register (DIR)
Configuration Control Register (CCR)
shows the addresses required to access these
3
HDSEL
0
2
nINDX
N/A
1
nWP
N/A
Rev 0.2 (09-28-04)
0
DIR
0