SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 175

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Chapter 16 Watchdog Timer
SMSC SCH311X
The SCH311X contains a Watchdog Timer (WDT). The Watchdog Time-out status bit may be mapped
to an interrupt through the WDT_CFG Runtime Register.
The SCH311X WDT has a programmable time-out ranging from 1 to 255 minutes with one minute
resolution, or 1 to 255 seconds with 1 second resolution. The units of the WDT timeout value are
selected via bit[7] of the WDT_TIMEOUT register. The WDT time-out value is set through the
WDT_VAL Runtime register. Setting the WDT_VAL register to 0x00 disables the WDT function (this
is its power on default). Setting the WDT_VAL to any other non-zero value will cause the WDT to
reload and begin counting down from the value loaded. When the WDT count value reaches zero the
counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Runtime register. Note:
Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared
by the Host CPU.
Two system events can reset the WDT: a Keyboard Interrupt or a Mouse Interrupt. The effect on the
WDT for each of these system events may be individually enabled or disabled through bits in the
WDT_CFG Runtime register. When a system event is enabled through the WDT_CFG register, the
occurrence of that event will cause the WDT to reload the value stored in WDT_VAL and reset the
WDT time-out status bit if set. If both system events are disabled, the WDT_VAL register is not re-
loaded.
The Watchdog Timer may be configured to generate an interrupt on the rising edge of the Time-out
status bit. The WDT interrupt is mapped to an interrupt channel through the WDT_CFG Runtime
register. When mapped to an interrupt the interrupt request pin reflects the value of the WDT time-
out status bit.
The host may force a Watchdog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force
WD Time-out) Runtime register. Writing a "1" to this bit forces the WDT count value to zero and sets
bit 0 of the WDT_CTRL (Watchdog Status). Bit 2 of the WDT_CTRL is self-clearing.
See the
Chapter 26, "Runtime Register," on page 293
DATASHEET
159
for description of these registers.
Rev 0.2 (09-28-04)