SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 59

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
DT1
0
1
0
1
DATA RATE
2 Mbps
1 Mbps
500 Kbps
300 Kbps
250 Kbps
7
RQM
1
DRIVE RATE
DT0
0
0
1
1
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
Note: The DRATE and DENSEL values are mapped onto the DRVDEN pins.
MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register and indicates the status of the disk controller. The
Main Status Register can be read at any time. The MSR indicates when the disk controller is ready
to receive data via the Data Register. It should be read before each byte transferring to or from the
data register except in DMA mode. No delay is required when reading the MSR after a data transfer.
Bit 0 DRV0 BUSY
This bit is set to 1 when a drive is in the seek portion of a command, including implied and overlapped
seeks and re calibrates.
6
DIO
0
DRVDEN1 (1)
DRATE0
DRATE0
DRATE0
DRATE1
5
NON DMA
1
DATA RATE
Table 7.8 Default Precompensation Delays
Table 7.6 Data Rates (continued)
Table 7.7 DRVDEN Mapping
0
4
CMD
BUSY
DATASHEET
DRVDEN0 (1)
DENSEL
DRATE1
nDENSEL
DRATE0
PRECOMPENSATION DELAYS
20.8 ns
41.67 ns
125 ns
125 ns
125 ns
250
43
DATA RATE
3
Reserved
125
2
Reserved
DRIVE TYPE
4/2/1 MB 3.5”
2/1 MB 5.25” FDDS
2/1.6/1 MB 3.5” (3-MODE)
PS/2
DENSEL
0
Reserved
1
1
DRATE(1)
Rev 0.2 (09-28-04)
DRV0
0
BUSY
0