SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 348

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
Keyboard
PWRBTN/SPEKEY
Default = 6Ch on
Vbat POR
Default = 0xxxxxxxb
on VTR POR, VCC
POR, and PCI
Reset
Note: The ‘x’
indicates bit is not
effected by reset
Keyboard
PWRBTN/SPEKEY
(continued)
WDT_TIME_OUT
Default = 0x00
on VCC POR, VTR
POR, and PCI
Reset
WDT_VAL
Default = 0x00
on VCC POR, VTR
POR, and PCI
Reset
NAME
Table 26.3 Detailed Runtime Register Description (continued)
64
R/W
when Bit [7]
is ‘0’
Read Only
when Bit [7]
is ‘1’
65
(R/W)
66
(R/W)
OFFSET
(HEX)
REG
Bit[0] SMSC Reserved bit. Must be written as a ‘0’.
Bit[1] SMSC Reserved bit. Must be written as a ‘0’.
Bits[3:2] SPEKEY ScanCode. This bit is used to configure the hardware
to decode a particular type of scan code.
00 = Single Byte, Scan Code Set 1 (Ex. make=37h and break=B7h)
01 =Multi-Byte, Scan Code Set 1 (Ex. make = E0h, 37h and break = E0h,
B7h)
10 = Single Byte, Scan Code Set 2 (Ex. make=37h and break=F0h 37h)
11 = Multi-Byte, Scan Code Set 2 (Ex. make = E0h, 37h and break = E0h
F0h 37h) (Default)
Bits[5:4] Keyboard Power Button Release
These bits are used to determine the pulse width of the Power Button event
from the keyboard (KB_PB_STS). The wake on specific key can be
configured to generate a PME event and/or power button event. If it is
used to generate a power button event, the following bits will determine
when the KB_PB_STS event is de-asserted.
00=De-assert KB_PB_STS 0.5sec after it is asserted (default)
01=De-assert KB_PB_STS after any valid scan code NOT EQUAL to the
programmed make code.
10=De-assert KB_PB_STS when scan code received is equal to
programmed break code
11=Reserved
Bit[6] SMSC Reserved bit. Must be written as a ‘1’.
Bit [7] Keyboard PWRBTN/SPEKEY Lock (Note) (This bit is Reset on a
Vbat POR, VTR POR, VCC POR, and PCI Reset)
0 = Keyboard PWRBTN/SPEKEY and Keyboard Scan Code Registers are
Read/Write
1 = Keyboard PWRBTN/SPEKEY and Keyboard Scan Code Registers are
Read Only
Note:
Keyboard Scan Code – Make Byte 1 at offset 5Fh
Keyboard Scan Code – Make Byte 2 at offset 60h
Keyboard Scan Code – Break Byte 1 at offset 61h
Keyboard Scan Code – Break Byte 2 at offset 62h
Keyboard Scan Code – Break Byte 3 at offset 63h
Keyboard PWRBTN/SPEKEY at offset 64h
Watch-dog Timeout
Bit[0] Reserved
Bit[1] Reserved
Bits[6:2] Reserved, = 00000
Bit[7] WDT Time-out Value Units Select
= 0 Minutes (default)
= 1 Seconds
Watch-dog Timer Time-out Value
Binary coded, units = minutes (default) or seconds, selectable via Bit[7] of
WDT_TIME_OUT register (0x52).
0x00 Time out disabled
0x01 Time-out = 1 minute (second)
.........
0xFF Time-out = 255 minutes (seconds)
DATASHEET
The following registers become Read-Only when Bit [7] is ‘1’:
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
332
DESCRIPTION
SMSC SCH311X
Datasheet