SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 149

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
12.7
12.8
DESCRIPTION
KCLK
KDAT
MCLK
MDAT
Host I/F Data Reg
Host I/F Status Reg
Note:
N/A = Not Applicable
OBF
The SCH311X Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz
clock. The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement
applies to both internally (VCC POR) and externally generated reset signals. In power-down mode,
the external clock signal is not loaded by the chip.
The SCH311X has one source of hardware reset: an external reset via the PCI_RESET# pin. Refer
to
GATEA20 AND KEYBOARD RESET
The SCH311X provides two options for GateA20 and Keyboard Reset: 8042 Software Generated
GateA20 and KRESET and Port 92 Fast GateA20 and KRESET.
PORT 92 FAST GATEA20 AND KEYBOARD RESET
Port 92 Register
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register
(Logical Device 7, 0xF0) set to 1.
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.
External Clock Signal
Default Reset Conditions
Table 12.4
When the SCH311X CPU reads the input data register (DBB), this bit is automatically reset
and the interrupt is cleared. There is no output pin associated with this internal signal.
register (DBB). When the host system reads the output data register, this bit is automatically
reset.
(Output Buffer Full) - This flag is set to whenever the SCH311X CPU write to the output data
for the effect of each type of reset on the internal registers.
Table 12.4 Resets
DATASHEET
133
HARDWARE RESET (PCI_RESET#)
Low
Low
Low
Low
N/A
00H
Rev 0.2 (09-28-04)