SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 108

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
NOTES ON SERIAL PORT OPERATION
FIFO Mode Operation:
General
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.
TX AND RX FIFO OPERATION
The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx
FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading
to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift
register. These capabilities account for the largely autonomous operation of the Tx.
The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt
whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance.
Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO
the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed
of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift
register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and
typically the UART’s interrupt line would transition to the active state. This could cause a system with
an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently
servicing that interrupt. Therefore, after the first byte has been loaded into the FIFO the UART
will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt.
This one character Tx interrupt delay will remain active until at least two bytes have been
loaded into the FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx
interrupt will be activated without a one character delay.
Rx support functions and operation are quite different from those described for the transmitter. The
Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level.
At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO
will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full.
Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth
and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an
overrun occurs.
One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data
level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the
trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To
prevent the software from having to check for this situation the chip incorporates a timeout
interrupt.
The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU
nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The
timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it.
These FIFO related features allow optimization of CPU/UART transactions and are especially useful
given the higher baud rate capability (256 kbaud).
TXD2 PIN
The TXD2 signal is located on the GP53/TXD2(IRTX) pin. The operation of this pin following a power
cycle is defined in
Section 8.1.1, "IR Transmit Pin," on page
93.
8.1
Infrared Interface
The infrared interface provides a two-way wireless communications port using infrared as a
transmission medium. Two IR implementations have been provided for the second UART in this chip
(logical device 5), IrDA and Amplitude Shift Keyed IR. The IR transmission can use the standard
UART2 TXD2 and RXD2 pins. These can be selected through the configuration registers.
Rev 0.2 (09-28-04)
92
SMSC SCH311X
DATASHEET