SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 166

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
13.6
13.7
GP60, GP61 are controlled by PME_STS6, and PME_EN6 registers.
The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status
and enable registers.
GP21, GP22, GP54, GP55, GP56, GP57, GP60 are controlled by SMI_STS3, and SMI_EN3 registers.
GP32, GP33, GP42, GP61 are controlled by SMI_STS4, and SMI_EN4 registers.
The following GPIOs have "either edge triggered interrupt" (EETI) input capability: GP21, GP22, GP60,
GP61. These GPIOs can generate a PME and an SMI on both a high-to-low and a low-to-high edge
on the GPIO pin. These GPIOs have a status bit in the PME_STS1 status register that is set on both
edges. The corresponding bits in the PME and SMI status registers are also set on both edges.
Three GPIO pins are implemented such that they allow an interrupt (PME or SMI) to be generated on
both a high-to-low and a low-to-high edge transition, instead of one or the other as selected by the
polarity bit.
The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the
GPIO pin, then the bits that control input/output, polarity and open drain/push-pull have no effect on
the function of the pin. However, the polarity bit does affect the value of the GP bit (i.e., register
PME_STS1, bit 2 for GP22).
A PME or SMI interrupt occurs if the PME or SMI enable bit is set for the corresponding GPIO and
the EETI function is selected on the GPIO. The PME or SMI status bits are set when the EETI pin
transitions (on either edge) and are cleared on a write of '1'. There are also status bits for the EETIs
located in the PME_STSX register, which are also cleared on a write of '1'. The MSC_STS register
provides the status of all of the EETI interrupts within one register. The PME, SMI or MSC status is
valid whether or not the interrupt is enabled and whether or not the EETI function is selected for the
pin.
Miscellaneous Status Register (MSC_STS) is for the either edge triggered interrupt status bits. If the
EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the
corresponding MSC status bits. Status bits are cleared on a write of '1'. See
Register," on page 293
The configuration register for the either edge triggered interrupt status bits is defined in
"Runtime Register," on page
The SCH311X provides LED functionality on two GPIOs, GP60 and GP61. These pins can be
configured to turn the LED on and off and blink independent of each other through the LED1 and LED2
runtime registers at offset 0x5D and 0x5E from the base address located in the primary base I/O
address in Logical Device A.
The LED pins (GP60 and GP61) are able to control the LED while the part is under VTR power with
VCC removed. In order to control a LED while the part is under VTR power, the GPIO pin must be
configured for the LED function and either open drain or push-pull buffer type. In the case of open-
drain buffer type, the pin is capable of sinking current to control the LED.
buffer type, the part will source current. The part is also able to blink the LED under VTR power. The
LED will not blink under VTR power (VCC removed) if the external 32KHz clock is not connected.
The LED pins can drive a LED when the buffer type is configured to be push-pull and the part is
powered by either VCC or VTR, since the buffers for these pins are powered by VTR. This means they
will source their specified current from VTR even when VCC is present.
The LED control registers are defined in
Either Edge Triggered Interrupts
LED Functionality
for more information.
293.
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Chapter 26, "Runtime Register," on page
150
In the case of push-pull
Chapter 26, "Runtime
293.
SMSC SCH311X
Chapter 26,
Datasheet