SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 122

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
3. The chip tri-states the PData bus and deasserts nWRITE.
4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and
5. Peripheral drives PData bus valid.
6. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination
7.
a. The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB
b. The chip drives the sync that indicates that no more wait states are required and drives valid data
8. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is
9. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes
are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is
in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by
the SPP Control Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from
the start of the EPP cycle to the end of the cycle. If a time-out occurs, the current EPP cycle is aborted
and the time-out condition is indicated in Status bit 0.
SOFTWARE CONSTRAINTS
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and
D3 are set to zero. Also, bit D5 (PCD) is a logic “0” for an EPP write or a logic “1” for and EPP read.
EPP 1.7 WRITE
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or
Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during
the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT
is inactive high.
Write Sequence of Operation
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EPP 1.7 READ
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip
inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can
be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high.
the nWRITE signal is valid.
phase of the cycle.
or nADDRSTRB. This marks the beginning of the termination phase.
onto the LAD[3:0] signals, followed by the TAR to complete the read cycle.
tri-stated.
The host sets PDIR bit in the control register to a logic “0”. This asserts nWRITE.
The host initiates an I/O write cycle to the selected EPP register.
The chip places address or data on PData bus.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and
the WRITE signal is valid.
If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts
nWAIT or a time-out occurs.
The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from
the internal data bus for the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
106
SMSC SCH311X
Datasheet