SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 180

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
Internal THERMTRIP#
18.1
Threshold1
Threshold2
Threshold
3.3VTR
PWRGD_PS
3.3V
nFPRST
RESETB
CLKI32
PS_ON
5V
RESET
RESET
The watchdog timer is a mechanism to monitor the host’s activity. It is part of the reset generation
circuitry. The Watchdog timer has the following characteristics:
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■
■
■
■
■
■
■
Watchdog Timer for Reset Generation
#
#
Figure 18.1 Reset Generation Circuit (For Illustrative Purposes Only)
Feature enable/disable via a bit in a control register, accessible from the LPC. When enabled, WDT
output is selected as a source for the PWRGD_OUT signal.
Watchdog input bit in a the RESGEN register, WDT2_CTL, reset to 0 via VCC_POR, accessible
from the LPC. See
Counts upto 1.6 sec
Counter reset by VCC_POR. The counter will remain reset as long as VCC_POR is active.
Counter will start as soon as VCC_POR is released, and the toggle bit is set to one.
If the host toggles the WDT2_CTL bit in control register, then counter is reset to 1.6 seconds and
begins to count again.
If the host does not toggle the WDT2_CTL bit in the control register before the WDT has timed out,
a 125 msec pulse is output.
After a timeout has occurred, a new timeout cycle does not begin until the host toggles the
WDT2_CTL bit in control register. This causes the counter to be reset to 1.6 seconds and begins
to count again
Set to '1' for SCH3116
Comparator
Reset Logic
Comparator
Reset Logic
Comparator
Reset Logic
and
and
and
Debounce
approx 140 msec Delay
Table
VCC_PORB
18.2.
RESGEN Bit[1]
THERMTRIP
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
SEL
164
WDT2_CTL
RESGEN
msec)
WDT
(125
Bit[2]
Strap = 1: 200 msec Delay
Strap = 0: 500 msec Delay
(Delays are approximate)
WDT2_EN
RESGEN
Bit[0]
PWROK
RSMRST#
SMSC SCH311X
Datasheet
PWRGD_OUT