SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 120

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Bit 5 PCD - PARALLEL CONTROL DIRECTION
Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out
regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer
port is in output mode (write); a logic 1 means that the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be written.
EPP ADDRESS PORT
ADDRESS OFFSET = 03H
The EPP Address Port is located at an offset of ‘03H’ from the base address. The address register
is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus
DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle
causes an EPP ADDRESS WRITE cycle to be performed, during which the data is latched for the
duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O
read cycle causes an EPP ADDRESS READ cycle to be performed and the data output to the host
CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register
is only available in EPP mode.
EPP DATA PORT 0
ADDRESS OFFSET = 04H
The EPP Data Port 0 is located at an offset of ‘04H’ from the base address. The data register is
cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus
DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle
causes an EPP DATA WRITE cycle to be performed, during which the data is latched for the duration
of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle
causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of
DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP
mode.
EPP DATA PORT 1
ADDRESS OFFSET = 05H
The EPP Data Port 1 is located at an offset of ‘05H’ from the base address. Refer to EPP DATA PORT
0 for a description of operation. This register is only available in EPP mode.
EPP DATA PORT 2
ADDRESS OFFSET = 06H
The EPP Data Port 2 is located at an offset of ‘06H’ from the base address. Refer to EPP DATA PORT
0 for a description of operation. This register is only available in EPP mode.
EPP DATA PORT 3
ADDRESS OFFSET = 07H
The EPP Data Port 3 is located at an offset of ‘07H’ from the base address. Refer to EPP DATA PORT
0 for a description of operation. This register is only available in EPP mode.
EPP 1.9 OPERATION
When the EPP mode is selected in the configuration register, the standard and bi-directional modes
are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is
in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by
the SPP Control Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from
Rev 0.2 (09-28-04)
104
SMSC SCH311X
DATASHEET