SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 126

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
NAME
PError
(nAckReverse)
Select
nAutoFd
(HostAck)
nFault
(nPeriphRequest)
nInit
nSelectIn
REGISTER DEFINITIONS
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer
ports are supported. The additional registers attach to an upper bit decode of the standard LPT port
definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port
interface and may be operated in that mode. The port registers vary depending on the mode field in
the ecr.
specified is undefined.
Table 9.4
TYPE
I
I
O
I
O
O
Table 9.3 ECP Pin Descriptions (continued)
lists these dependencies. Operation of the devices in modes other that those
DESCRIPTION
Used to acknowledge a change in the direction the transfer (asserted =
forward).
nReverseRequest. It is an “interlocked” handshake with nReverseRequest.
The host relies upon nAckReverse to determine when it is permitted to drive
the data bus.
Indicates printer on line.
Requests a byte of data from the peripheral when asserted, handshaking with
nAck in the reverse direction. In the forward direction this signal indicates
whether the data lines contain ECP address or data. The host drives this
signal to automatic direction control in the reverse direction. It is an
“interlocked” handshake with nAck. HostAck also provides command
information in the forward phase.
Generates an error interrupt when asserted. This signal provides a mechanism
for peer-to-peer communication. This signal is valid only in the forward
direction. During ECP Mode the peripheral is permitted (but not required) to
drive this pin low to request a reverse transfer. The request is merely a “hint”
to the host; the host has ultimate control over the transfer direction. This
signal would be typically used to generate an interrupt to the host CPU.
Sets the transfer direction (asserted = reverse, deasserted = forward). This
pin is driven low to place the channel in the reverse direction. The peripheral
is only allowed to drive the bi-directional data bus while in ECP Mode and
HostAck is low and nSelectIn is high.
Always deasserted in ECP mode.
The peripheral drives this signal low to acknowledge
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
110
SMSC SCH311X
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