SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 270

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
24.2.29
24.2.30
Register
Address
Register
Address
80h
81h
Read/
Write
R/W
Read/
Write
R/W
Register 80h: Interrupt Enable 2 Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to enable individual fan tach error events to set the corresponding status bits in
the interrupt status registers. This register also contains the group fan tach enable bit (Bit[0] TACH),
which is used to enable fan tach events to force the interrupt pin (nHWM_INT) low if interrupts are
enabled (see Bit[2] INTEN of the Special Function register at offset 7Ch).
This register contains the following bits:
Bit[0] FANTACH (Group TACH Enable)
0=Out-of-limit tachometer readings do not affect the state of the nHWM_INT pin (default)
1=Enable out-of-limit tachometer readings to make the nHWM_INT pin active low
Bit[1] Fantach 1 Event Enable
Bit[2] Fantach 2 Event Enable
Bit[3] Fantach 3 Event Enable
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The individual fan tach error event bits are defined as follows:
0=disable
1=enable.
See PME_STS1.
Register 81h: TACH_PWM Association Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to associate a PWM with a tachometer input. This association is used by the fan
logic to determine when to prevent a bit from being set in the interrupt status registers.
The fan tachometer will not cause a bit to be set in the interrupt status register:
a. if the current value in Current PWM Duty registers is 00h or
b. if the fan is disabled via the Fan Configuration Register.
Interrupt Enable 2 (Fan
Register Name
TACH_PWM Association
Tachs)
Register Name
(MSb)
Bit 7
RES
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
(MSb)
Bit 6
RES
Bit 7
RES
254
Bit 5
RES
Bit 6
RES
Bit 5
T3H
Bit 4
RES
Bit 4
T3L
FANTA
Bit 3
CH3
Bit 3
T2H
FANTA
Bit 2
CH2
Bit 2
T2L
FANTA
Bit 1
CH1
Bit 1
T1H
TACH
(LSb)
SMSC SCH311X
(LSb)
FAN-
Bit 0
Bit 0
T1L
Datasheet
Default
Default
Value
Value
1Eh
24h