SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 121

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
the start of the EPP cycle to nWAIT being deasserted (after command). If a time-out occurs, the
current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to
always be in a write mode and the nWRITE signal to always be asserted.
SOFTWARE CONSTRAINTS
Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic
“0” (i.e., a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic “1”,
and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic
“1”) and will appear to perform an EPP read on the parallel bus, no error is indicated.
EPP 1.9 WRITE
The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or
Address cycle. The chip inserts wait states into the LPC I/O write cycle until it has been determined
that the write cycle can complete.
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Write Sequence of operation
1. The host initiates an I/O write cycle to the selected EPP register.
2. If WAIT is not asserted, the chip must wait until WAIT is asserted.
3. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.
4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and
5. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the
6.
a. The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase.
b. The chip latches the data from the internal data bus for the PData bus and drives the sync that
7. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been
8. Chip may modify nWRITE and nPDATA in preparation for the next cycle.
EPP 1.9 READ
The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip
inserts wait states into the LPC I/O read cycle until it has been determined that the read cycle can
complete. The read cycle can complete under the following circumstances:
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Read Sequence of Operation
1. The host initiates an I/O read cycle to the selected EPP register.
2. If WAIT is not asserted, the chip must wait until WAIT is asserted.
If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then
the write can complete when nWAIT goes inactive high.
If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low
before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once
nWAIT is determined inactive.
the WRITE signal is valid.
chip may begin the termination phase of the cycle.
If it has not already done so, the peripheral should latch the information byte now.
indicates that no more wait states are required followed by the TAR to complete the write cycle.
satisfied and acknowledging the termination of the cycle.
If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can
complete when nWAIT goes inactive high.
If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low
before changing the state of nWRITE or before nDATASTB goes active. The read can complete
once nWAIT is determined inactive.
DATASHEET
The write cycle can complete under the following circumstances:
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Rev 0.2 (09-28-04)