SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 188

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
20.3
Internal nFPRST
(after debounce)
debounce)
nFPRST
(before
Devices only)
A/C Power Failure Recovery Control (SCH3112 and SCH3114
The Power Failure Recovery Control logic, which is powered by VTR, is used to return a system to a
pre-defined state after a power failure (VTR=0V). The Power Control Register, which is powered by
Vbat, contains two bits defined as APF (After Power Failure). These bits are used to determine if the
power supply should be powered on, powered off, or set to the previous power state before VTR was
removed as shown in
Power Failure Recovery registers that are required to retain their state through a power failure are
powered by Vbat.
Two modes may be used to determine the previous state:
Mode 1: (Suggested if PWR_OK is selected& enabled), which is enabled when Bit[3] PS_ON#
sampling is disabled, latches the current value of the PS_ON# pin when VCC, VTR, or PWR_OK (if
enabled) transition to the inactive state, whichever comes first. This value is latched into Bit[4]
Previous State Bit located in the Power Recovery Register located at offset 49h and is used to
determine the state of the PS_ON# pin when VTR becomes active.
Mode 2 is enabled when Bit[3] PS_ON# sampling is enabled. To determine the previous power state,
the PS_ON# pin is sampled every 0.5 seconds while VTR is greater than ~2.2Volts. This sample is
inserted into a battery powered 8-bit shift register. The hardware will select a bit from the shift register
depending on the value of the PS_ON# Previous State Select bits located in the Runtime Register
block at offset 53h to determine the state of the PS_ON# pin when VTR becomes active. The value
in the 8-bit shift register is latched into the PS_ON Register at offset 4Ah in the Runtime Register block
after VTR power is returned to the system, but before the internal shift register is cleared and activated.
The PS_ON Register is a battery powered register that is only reset on a Vbat POR.
Notes:
■
In Mode 2, when VTR falls below ~2.2Volts the current value of the PS_ON# pin will be latched
into Bit [4] Previous State Bit located in the Power Recovery Register at offset 49h. This bit will
Press
Figure 20.2 nFPRST Debounce Timing
Table
15.8msec
20.3.
min
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
172
Release
15.8msec
will be detected
min
nFPRST press
starting here
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SMSC SCH311X
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