SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 204

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
23.3
23.4
23.4.1
23.4.2
The HWM block is powered by standby power, HVTR, to retain the register settings during a main
power (sleep) cycle. The HWM block does not operate when VCC=0 and HVTR is on. In this case,
the H/W Monitoring logic will be held in reset and no monitoring or fan control will be provided.
Following a VCC POR, the H/W monitoring logic will begin to operate based on programmed
parameters and limits.
The fan tachometer input pins are protected against floating inputs and the PWM output pins are held
low when VCC=0.
Note: The PWM pins will be forced to “spinup” (if enabled) when PWRGD_PS goes active. See
VTR Power-On Reset
All the registers in the Hardware Monitor Block, except the reading registers, reset to a default value
when VTR power is applied to the block. The default state of the register is shown in the Register
Summary Table located in PME_STS1. The default state of Reading Registers are not shown because
these registers have indeterminate power on values.
Note: Usually the first action after power up is to write limits into the Limit Registers.
VCC Power-On Reset
The PWRGD_PS signal is used by the hardware-monitoring block to determine when a VCC POR has
occurred. The PWRGD_PS signal indicates that the VCC power supply is within operation range and
the 14.318MHz clock source is valid.
Power Supply
Resetting the SCH311X Hardware Monitor Block
base + 70h
base + 71h
“PWM Fan Speed Control” on page 200.
Logical Device 0Ah
Runtime Registers
HWM_Index
HWM_Data
Figure 23.2 HWM Register Access
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
188
hwm registers
FFh
00h
SMSC SCH311X
Datasheet