SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 124

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
9.2
ecpAFifo
cFifo
data
dsr
dcr
ECP provides a number of advantages, some of which are listed below. The individual features are
explained in greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable
transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for
low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers
permits the use of adaptive signal timing Peer-to-peer capability.
VOCABULARY
The following terms are used in this document:
assert:
forward:
reverse:
Pword:
1
0
These terms may be considered synonymous:
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard ,
Rev 1.14, July 14, 1993. This document is available from Microsoft.
The bit map of the Extended Parallel Port registers is:
Extended Capabilities Parallel Port
D7
Addr/RLE
nBusy
PD7
0
to a "false" state.
PWord is always 8 bits.
When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions
Host to Peripheral communication.
Peripheral to Host communication
A port word; equal in size to the width of the LPC interface. For this implementation,
A high level.
A low level.
D6
nAck
PD6
0
D5
Direction
PError
PD5
Parallel Port Data FIFO
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
D4
ackIntEn
Select
Address or RLE field
PD4
108
D3
SelectI
nFault
PD3
n
D2
PD2
nInit
0
D1
autofd
PD1
0
D0
strobe
PD0
0
SMSC SCH311X
Datasheet
NOTE
2
1
1
2