SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 269

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
APPLICATION NOTE: When the START bit is 1, and the device is monitoring, this bit will toggle each time it
SMSC SCH311X
24.2.28
Register
Address
7Fh
/Write
Read
R/W
The individual voltage error event bits are defined as follows:
0=disable
1=enable.
See
Register 7Fh: Configuration Register
Note 24.18 TRDY is cleared when the PWRGD_PS signal is asserted.
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register contains the following bits:
Bit[0] Reserved
Bit[1] Reserved
Bit[2] MON_DN: This bit is used to detect when the monitoring cycle is completed following the START
bit being set to 0. When the START bit is cleared, the hardware monitoring block always completes
the monitoring cycle. 0= monitoring cycle active, 1= monitoring cycle complete.
Bit[3] TRDY: Temperature Reading Ready. This bit indicates that the temperature reading registers
have valid values. This bit is used after writing the start bit to ‘1’. 0= not valid, 1=valid.
Bit[4] SUREN: Spin-up reduction enable. This bit enables the reduction of the spin-up time based on
feedback from all fan tachometers associated with each PWM. 0=disable, 1=enable (default)
Bit[5] SMSC Reserved
This is an SMSC Reserved bit. Writing this bit to a value different than the default value may cause
unwanted results.
Bit[5] SMSC Reserved
This is an SMSC Reserved bit. Writing this bit to a value different than the default value may cause
unwanted results.
Bit[6] SMSC Reserved
This is an SMSC Reserved bit. Writing this bit to a value different than the default value may cause
unwanted results.
Bit[7] Initialization
Setting the INIT bit to ‘1’ performs a soft reset. This bit is self-clearing. Soft Reset sets all the registers
except the Reading Registers to their default values.
Figure 23.3 Interrupt Control on page
Register Name
Configuration
completes the monitoring cycle. It is intended that the user only read this bit when the START
bit is 0.
(MSb)
Bit 7
INIT
SMSC
Bit 6
DATASHEET
SMSC
253
Bit 5
193.
SUREN
Bit 4
TRDY
24.18
Bit 3
Note
MON_
Bit 2
DN
Bit 1
RES
Rev 0.2 (09-28-04)
(LSb)
Bit 0
RES
Default
Value
10h