SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 134

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
DATA COMPRESSION
The ECP port supports run length encoded (RLE) decompression in hardware and can transfer
compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not
supported. To transfer compressed data in ECP mode, the compression count is written to the
ecpAFifo and the data byte is written to the ecpDFifo.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates
how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and
repeats the following byte the specified number of times. When a run-length count is received from a
peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of
zero specifies that only one byte of data is represented by the next data byte, whereas a run-length
count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion,
however, run-length counts of zero should be avoided.
PIN DEFINITION
The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-drain in mode 000 and are push-pull
in all other modes.
LPC CONNECTIONS
The interface can never stall causing the host to hang. The width of data transfers is strictly controlled
on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and
end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A,
cnfgA, described in the next section). Single byte wide transfers are always possible with standard or
PS/2 mode using program control of the control signals.
INTERRUPTS
The interrupts are enabled by serviceIntr in the ecr register.
serviceIntr = 1
serviceIntr = 0
An interrupt is generated when:
1. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received.
2. For Programmed I/O:
a. When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes
b. When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in
3. When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0
4. When ackIntEn is 1 and the nAck signal transitions from a low to a high.
FIFO OPERATION
The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel
port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode.
The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test
mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred
by a Programmed I/O cycle or DMA cycle depending on the selection of DMA or Programmed I/O
mode.
in the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are
writeIntrThreshold or more free bytes in the FIFO.
the FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are
readIntrThreshold or more bytes in the FIFO.
and nFault is asserted.
Disables the DMA and all of the service interrupts.
Enables the selected interrupt condition.
the interrupts generated immediately when this bit is changed from a 1 to a 0. This
can occur during Programmed I/O if the number of bytes removed or added from/to
the FIFO does not cross the threshold.
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
118
If the interrupting condition is valid, then
SMSC SCH311X
Datasheet