SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 328

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
SMI_EN2
Default = 0x00
SMI_EN3
Default = 0x00
SMI_EN4
Default = 0x00
THIS IS FOR THE
SCH3112 DEVICE
ONLY
SMI_EN4
Default = 0x00
THIS IS FOR THE
SCH3114 DEVICE
ONLY
on VTR POR
on VTR POR
on VTR POR
on VTR POR
NAME
Table 26.3 Detailed Runtime Register Description (continued)
19
(R/W)
1A
(R/W)
1B
(R/W)
1B
(R/W)
OFFSET
(HEX)
REG
SMI Enable Register 2
This register is used to enable the different interrupt sources onto the group
nSMI output, and the group nSMI output onto the nIO_SMI GPI/O pin, the
serial IRQ stream or into the PME Logic.
Unless otherwise noted,
1=Enable
0=Disable
Bit[0] EN_MINT
Bit[1] EN_KINT
Bit[2] EN_IRINT
Bit[3] Reserved
Bit[4] EN_SPESME
Bit[5] EN_SMI_PME (Enable group SMI into PME logic)
Bit[6] EN_SMI_S (Enable group SMI onto serial IRQ)
Bit[7] EN_SMI (Enable group SMI onto nIO_SMI pin)
SMI Enable Register 3
This register is used to enable the different interrupt sources onto the group
nSMI output.
1=Enable
0=Disable
Bit[0] Reserved
Bit[1] GP21
Bit[2] GP22
Bit[3] GP54
Bit[4] GP55
Bit[5] GP56
Bit[6] GP57
Bit[7] GP60
SCH3112 Device
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] RESERVED
Bit[1] RESERVED
Bit[2] GP32
Bit[3] GP33
Bit[4] RESERVED
Bit[5] GP42
Bit[6] RESERVED
Bit[7] GP61
SCH3114 Device Only:
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] U3INT
Bit[1] U4INT
Bit[2] GP32
Bit[3] GP33
Bit[4] RESERVED
Bit[5] GP42
Bit[6] RESERVED
Bit[7] GP61
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
312
DESCRIPTION
SMSC SCH311X
Datasheet