SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 271

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
24.2.31
Register
Address
82h
BITS[1:0], BITS[3:2], BITS[5:4], BITS[7:6]
/Write
Read
R/W
Note: A bit will never be set in the interrupt status for a fan if its tachometer minimum is set to FFFFh.
See bit definition below.
Bits[1:0] Tach1. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[3:2] Tach2. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[5:4] Tach3. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[7:6] Reserved
Notes:
■
■
Register 82h: Interrupt Enable 3 Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to enable individual thermal error events to set the corresponding status bits in
the interrupt status registers. This register also contains the group thermal enable bit (Bit[0] TEMP),
which is used to enable thermal events to force the interrupt pin (nHWM_INT) low if interrupts are
enabled (see Bit[2] INTEN of the Special Function register at offset 7Ch).
This register contains the following bits:
Bit[0] TEMP. Group temperature enable bit.
0=Out-of-limit temperature readings do not affect the state of the nHWM_INT pin (default)
1=Enable out-of-limit temperature readings to make the nHWM_INT pin active low
Bit[1] ZONE 2 Temperature Status Enable bit.
Bit[2] ZONE 1 Temperature Status Enable bit.
Bit[3] ZONE 3 Temperature Status Enable bit
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1.
All TACH inputs must be associated with a PWM output. If the tach is not being driven by the
associated PWM output it should be configured to operate in Mode 1 and the associated TACH
interrupt must be disabled.
Interrupt Enable 3 (Temp)
00
01
10
11
Register
Name
DATASHEET
(MSb)
Bit 7
RES
255
Bit 6
RES
Bit 5
RES
PWM ASSOCIATED WITH TACHX
Bit 4
RES
D2EN
Bit 3
Reserved
PWM1
PWM2
PWM3
D1EN
Bit 2
Bit 1
AMB
Rev 0.2 (09-28-04)
TEMP
(LSb)
Bit 0
Default
Value
0Eh