MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 102

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

5–30
5.4.9
5.5
5.6
In NT mode, IDL2 slave operation, any superframe alignment information that may be present on
FSC is ignored. ANSI T1.601 defines a 60
mitted Superframe Sync word in the NT–configured MC145572 is delayed 60 bauds or 750 s from
the received Superframe Sync word. On an 18,000–foot loop, the total propagation delay in both direc-
tions is approximately 6 bauds or 39 s. This gives a worse case offset between the transmitted sync
word at LT and the receive sync word at NT of approximately 790 s or 6 IDL frames.
Initial State of B1 and B2 Channels
Upon initial activation, MC145572 transmits all 1s in the B and D channels onto the U–interface. Data
transparency is enabled by setting Customer Enable (NR2(b0)), when the M4 channel act bit is re-
ceived as a 1. If the Verified act/dea mode is enabled, see BR9(b5,b4), then data transparency onto
the U–interface is automatically enabled when the M4 channel act bit is received as a 1.
FRAME SYNC TO U-INTERFACE PROPAGATION DELAYS
Due to the MC145572 having separate FIFOs for receive and transmit directions, there is a propagation
delay between data being input into the IDL2 or GCI interfaces and that same data being transmitted
onto the U–interface. Likewise, there is a delay between when data is received at the U–interface
and is transmitted onto the IDL2 or GCI interfaces. Table 5–7 gives the minimum and maximum delays
for both NT and LT modes of operation. For any given activation, the delay remains fixed, but the
propagation delay through the MC145572 will vary from activation to activation.
LOOPBACKS
The MC145572 U–interface transceiver supports four different loopback types, each having various
modes. The four types are: 1) U–Interface Loopback, 2) IDL2 Interface Loopback, 3) Superframe
Framer–to–Deframer Loopback, and 4) External Analog Loopback. Each of these loopback modes
is selected by setting bits in the appropriate register(s). Any combination of loopbacks may be invoked,
including simultaneous loopbacks toward the U–interface and toward the IDL2 interface. These loop-
backs are available as transparent or non–transparent. “Transparent” means that a loopback passes
the data on through to the other side, as well as looping it back. “Non–transparent” means that the
data is blocked from being passed downstream and is replaced with the idle code (all 1s).
The total end–to–end delay is the sum of the transmit FIFO delay in the originating trans-
ceiver and the receive FIFO delay at the destination transceiver.
NT Mode FSX to U–Interface Transmission Delay
NT Mode U–Interface to FSR Transmission Delay
LT Mode FSX to U–Interface Transmission Delay
LT Mode U–Interface to FSR Transmission Delay
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5–7. FIFO Delays Through the MC145572
Delay Path
Go to: www.freescale.com
MC145572
2 baud turnaround at the NT. This means that the trans-
NOTE
Min
196
281
184
281
Max
315
400
328
400
Units
s
s
s
s
MOTOROLA