MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 71

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
4.6.1
4.6.2
4.6
2048 Disable
When this bit is set to 1, it causes the 20.48 MHz clock output at BUFXTAL to go to high impedance.
1536 Disable
When this bit is set to 1, it causes the 15.36 CLKOUT pin to go high impedance.
4096 Disable
When this bit is set to 1, it causes the 4.096 CLKOUT pin to go high impedance. This bit may only be
written to once, following a hardware or software reset. Once the 4.096 CLKOUT pin has been turned
off by setting this bit, it can only be re–enabled by asserting a hardware or software reset to the
MC145572. This bit is reset by hardware reset, NR0(b3) = 1 or NR0(b1) = 1.
D CHANNEL AND DEBUG REGISTERS
OR12: D Channel Data Register
When BR10(b1) is set to 1, this double buffered register takes the place of Normal Byte register BR12,
and the register becomes an 8–bit read–only/write–only register providing access to the D channel.
In this mode, D channel input data present on the pin interfaces of MC145572 is ignored. Instead,
D channel is sourced strictly from this register. D channel data received from U–interface is byte aligned
to Superframe Sync, and is readable through OR12, eight bits at a time. This register is updated with
the received D channel data, when SFS, NR1(b3) is a 1. Data is transferred from OR12 to the U–inter-
face, when SFS, NR1(b3), is a 1.
IRQ3 is used to indicate when each new eight bits of data are received. A special code (1111) is loaded
in Nibble register NR1, to indicate that the source of the interrupt is the D channel access register.
Reading OR12 clears the special code (1111) from NR1, but does not affect any updates in activation
status. So, if there has been a change in activation status, an interrupt is still queued up even though
the D channel interrupt has been cleared. Both transmit and receive D channel data are aligned to
the transmit and receive superframes. The MC145572 does not perform any HDLC framing/deframing.
D channel data is transmitted to and received from the U–interface most significant bit first.
OR13: Dump/Restore Test Register
This register takes the place of Byte register BR13 when BR10 B(2) is set, and the register becomes
a byte–wide access port to the dump/restore mechanism of the U–chip. Two more bits in the overlay
registers control the operating mode of the dump/restore mechanism. See Overlay register OR8. This
bit is reset by both hardware and software resets. After a hardware or software reset, all bits default
to 0 to maintain MC145472/MC14LC5472 compatibility.
OR12
OR13
If this register is used when the timeslot assignment is enabled, D channel timeslot must not
be 0, so as to maintain synchronization with the transmit superframe. This is especially im-
portant in LT mode, when SFAX is used as an input.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MC145572
D Channel Transmit Bits (7:0)
D Channel Transmit Bits (7:0)
Dump Register Write Access
Dump Register Read Access
NOTE
wo
wo
ro
ro
4–35