MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 134

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
NOTES:
8–10
8.3.2.2
8.3.2.3
b17
b17
1. If a maintenance channel is updated in the MC145572 receive deframer at the same time a register read command is received, then an
2. The bits a1 through a3, dm, and i1 through i8 are data that is read from the eoc register. The bits d7 through d0 are data that is read from
3. For non–ISDN applications, the data written to the eoc register uses the convention that bit a1 is the most significant bit and bit i8 is the
1. The bits a1 through a3, dm, and i1 through i8 are data that is read from eoc register R6.
2. For non–ISDN applications, the data read from the eoc register uses the convention that bit a1 is the most significant bit and bit i8 is the
3. The data byte returned by the M5/M6 interrupt corresponds to the byte as read from Byte register BR3 in the SCP interface mode register
4. The data byte returned by the M4 interrupt corresponds to the byte as read from Byte register BR1 in the SCP interface mode register map.
0
0
0
1
0
0
0
interrupt indication message is issued first. The indication message takes priority over requests for register reads. All queued interrupt indica-
tion messages are issued before the response to the register read message. It is important for software to always check the message code
in byte 1 of any received message.
a register.
least significant bit.
least significant bit.
map. The bits d7 through d0 are data that is read from a register.
b16
b16
0
0
1
0
0
0
1
MONITOR CHANNEL RESPONSE MESSAGES
The Monitor channel response messages are transmitted onto the GCI Monitor channel by the
MC145572 in response to a register read command. The Monitor channel response messages are
given in Table 8–4.
MONITOR CHANNEL INTERRUPT INDICATION MESSAGES
The Monitor channel interrupt indication messages are automatically transmitted onto the GCI Monitor
channel by the MC145572 when its receiver deframer updates one of the maintenance channel regis-
ters BR1, BR3, or eoc register R6. The maintenance channel registers are updated when the trinal
checking of bits or messages has been completed. All outstanding interrupt indication messages are
transmitted prior to any response messages being transmitted. The Monitor channel interrupt indication
messages are given in Table 8–5.
When a Monitor channel interrupt indication message is transmitted by the MC145572, the corre-
sponding internal register is read and the interrupt is automatically cleared.
b15
b15
0
1
0
0
0
1
0
b14
b14
1
1
1
0
0
0
0
Table 8–5. Monitor Channel Interrupt Indication Messages
b13
ba3
na3
b13
Table 8–4. Monitor Channel Response Messages
a1
a1
0
0
0
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b12
b12
ba2
na2
a2
a2
0
0
0
b11
ba1
na1
b11
a3
a3
0
0
0
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b10
b10
ba0
na0
dm
dm
0
0
0
MC145572
b27
b27
d7
d3
d7
d7
i1
i1
0
b26
b26
d6
d2
d6
d6
i1
i1
0
b25
b25
d5
d1
d5
d5
i3
i3
0
b24
b24
d4
d0
d4
d4
i4
i4
0
b23
b23
d3
d3
d3
i5
i5
0
x
b22
b22
d2
d2
d2
i6
i6
x
0
b21
b21
d1
d1
d1
i7
i7
x
0
b20
b20
d0
d0
d0
i8
i8
x
0
MOTOROLA
Identifi-
eoc int.
Device
M4 int.
M5/M6
Nibble
cation
Read
Read
Read
Byte
eoc
int.